Calvin Plett

The effect of varactor nonlinearity on the phase noise of completely integrated VCOs

This work discusses variations in phase noise over the tuning range of a completely integrated 1.9-GHz differential voltage-controlled oscillator (VCO) fabricated in a 0.5-/spl mu/m bipolar process with 25-GHz f/sub t/. The design had a phase noise of -103 dBc/Hz at 100 kHz offset at the top of the tuning range, but the noise performance degraded to -96 dBc/Hz at 100 kHz at the bottom of the tuning range. It was determined that nonlinearities of the on-chip varactors, which led to excessively high VCO gain at the bottom of the tuning range, were primarily responsible for this degradation in performance. The VCO has a power output of -5 dBm per side. Calculations predict phase noise with only a small error and provide design insight for minimizing this effect. The oscillator core drew 6.4 mA and the output buffer circuitry drew 6 mA, both from a 3.3-V supply.

An agile ISM band frequency synthesizer with built-in GMSK data modulation

In this paper, a high-resolution fractional-N RF frequency synthesizer is presented which is controlled by a fourth-order digital sigma-delta modulator. The high resolution allows the synthesizer to be digitally modulated directly at RF. A simplified digital filter which makes use of sigma-delta quantized tap coefficients is included which provides built-in GMSK pulse shaping for data transmission. Quantization of the tap coefficients to single-bit values not only simplifies the filter architecture, but the fourth-order digital sigma-delta modulator as well. The synthesizer makes extensive use of custom VLSI, with only a simple off-chip loop filter and VCO required. The synthesizer operates from a single 3-V supply, and has low power consumption. Phase noise levels are less than -90 dBc/Hz at frequency offsets within the loop bandwidth. Spurious components are less than -90 dBc/Hz over a 19.6-MHz tuning range.

A 0.18-

Current-mode circuits are presented for implementing analog min-sum (MS) iterative decoders. These decoders are used to efficiently decode the best known error correcting codes such as low-density parity-check (LDPC) codes and turbo codes. The proposed circuits are devised based on current mirrors, and thus, in any fabrication technology that accurate current mirrors can be designed, analog MS decoders can be implemented. The functionality of the proposed circuits is verified by implementing an analog MS decoder for a (32,8) LDPC code in a 0.18-mum CMOS technology. This decoder is the first reported analog MS decoder. For low signal to noise ratios where the circuit imperfections are dominated by the noise of the channel, the measured error correcting performance of this chip in steady-state condition surpasses that of the conventional floating-point discrete-time synchronous MS decoder. When data throughput is 6 Mb/s, loss in the coding gain compared to the conventional MS decoder at BER of 10-3 is about 0.3 dB and power consumption is about 5 mW. This is the first time that an analog decoder has been successfully tested for an LDPC code, though a short one

muhbox m

The design of a low-voltage 40-GHz complementary voltage-controlled oscillator (VCO) with 15% frequency tuning range fabricated in 0.13-/spl mu/m partially depleted silicon-on-insulator (SOI) CMOS technology is reported. Technological advantages of SOI over bulk CMOS are demonstrated, and the accumulation MOS (AMOS) varactor limitations on frequency tuning range are addressed. At 1.5-V supply, the VCO core and each output buffer consumes 11.25 mW and 3 mW of power, respectively. The measured phase noise at 40-GHz is -109.73 dBc/Hz at 4-MHz offset from the carrier, and the output power is -8 dBm. VCO performance using high resistivity substrate (/spl sim/300-/spl Omega//spl middot/cm) has the same frequency tuning range but 2 dB better phase noise compared with using low resistivity substrate (10 /spl Omega//spl middot/cm). The VCO occupies a chip area of only 100 /spl mu/m by 100 /spl mu/m (excluding pads).

CMOS Analog Min-Sum Iterative Decoder for a (32,8) Low-Density Parity-Check (LDPC) Code

This paper presents both analog and digital automatic-amplitude control techniques for voltage-controlled oscillators (VCOs). These feedback mechanisms help to keep the VCOs at an optimum amplitude over temperature, process, and voltage variations. The VCOs were fabricated in a 50-GHz SiGe BiCMOS process. They use MOS varactors and achieve a 600-MHz tuning range in the 2-GHz band. The phase noise of the VCO with analog control was measured to be -99 dBc/Hz at 100-kHz offset from the carrier. The digital loop allows for a more optimized VCO core that achieves a phase noise of -108.5 dBc/Hz at 100-kHz offset in a low-gain mode. Techniques for suppressing the phase noise in regions of high gain are also presented. The VCOs draw between 4 and 8 mA from a 3.3-V supply.

A low-voltage 40-GHz complementary VCO with 15% frequency tuning range in SOI CMOS technology

This paper reports a CMOS distributed amplifier which operates from 1-27 GHz. This amplifier exhibits a measured gain of 6 dB and uses coplanar waveguides to implement required inductances. Power consumption is 68.1 mW while driven from a 3.3V supply but it can operate with supply voltages as low as 1.8V. Chip area is 1.8 /spl times/ 0.9 mm. To the authors knowledge this is the fastest frequency of operation ever reported for a distributed amplifier implemented in a standard CMOS technology.

A study of digital and analog automatic-amplitude control circuitry for voltage-controlled oscillators

A simple post-processing technique allowing Cu inductors to be added to integrated circuits fabricated in technologies providing only Al metallization is presented. The inductors use a 4-/spl mu/m thick electroless plated Cu layer to minimize resistance, and are formed over a 9-/spl mu/m thick polyimide dielectric to reduce substrate losses. Inductors optimized for 2.5-GHz had Q as high as 17. The effectiveness of the post-processing technique is demonstrated by application to a voltage-controlled oscillator (VCO) fabricated in a commercial bipolar technology with Al metallization. Circuits with post-processed Cu inductors gave a phase noise of -106 dBf/Hz at 100 kHz offset from a 2-GHz carrier, while control circuits with Al inductors gave a phase noise of only -101 dBc/Hz at 100 kHz offset from a 1.8-GHz carrier and had higher power consumption.

A 27 GHz fully integrated CMOS distributed amplifier using coplanar waveguides

This paper presents a completely integrated, low-power 6.3 GHz oscillator transmitter which includes an on-chip antenna suitable for short-range medical sensor applications. The transmitter, implemented in a 1.2 V 0.13 mum CMOS process, utilizes open-loop direct VCO modulation for BFSK data at a rate of 300 kbps. For communicating a 1 kbit packet once per second, an average power consumption of 14 muW is achieved. During a packet transmission, the power consumption of the transmitter is 4.25 mW, enabling a self-powered design using integrated ultracapacitors for an SoC solution. With a radiated power of 0 dBm, the transmitter has a communication range of 2 m.

Post-processed Cu inductors with application to a completely integrated 2-GHz VCO

A low-voltage receiver front-end for 5-GHz radio applications is presented. The receiver consists of a low-noise amplifier (LNA) with notch filter, a voltage-controlled oscillator (VCO), and a mixer. The LNA/notch filter has an automatic Q-tuning circuit integrated with it to provide good image rejection. On-chip transformers are used extensively in the receiver to improve performance and facilitate low-voltage operation. The receiver has a gain of 19.8 dB, noise figure of 4.5 dB, a third-order input intercept point (IIP3) of -11.5 dBm, and an image rejection of 59 dB, and the VCO had a phase noise of -116 dBc/Hz at 1-MHz offset.

A 6.3 GHz BFSK Transmitter with On-Chip Antenna for Self-Powered Medical Sensor Applications

A solenoid layout technique is used to increase the magnetic coupling between the coils in multi-level spiral transformers. Using this technique, transformers with the following performance are measured: (a) magnetic coupling with coupling factor k>0.95 and insertion loss s/sub 21/ better than 0.8 dB at 5 GHz; (b) self-resonant frequency f/sub res/>15 GHz with peak Q>10. The effect of high and low resistive substrates is discussed with measured results. Using this structure, the size of the transformer can be reduced from 50 to 400%.