Nestoras E. Evmorfopoulos

A Monte Carlo approach for maximum power estimation based on extreme value theory

A Monte Carlo approach for maximum power estimation in CMOS very large scale integration (VLSI) circuits is proposed. The approach is based on the largely unexploited area of statistics known as extreme value theory. Within this framework, it attempts to appropriately model the extreme behavior of the probability distribution of the peak instantaneous power drawn from the power supply bus, in order to yield a close estimate of its maximum possible value. The approach features a relatively small number of necessary input patterns that does not depend on the circuit size, user-specified accuracy, and confidence levels for the final estimate, simplicity in the algorithmic implementation, noniterative single-loop execution, highly accurate simulation-based operation, and easy integration within the design flow of CMOS VLSI circuits. Experimental results establish the above claims and demonstrate the overall efficiency of the proposed approach to address the problem of maximum power estimation.

Precise identification of the worst-case voltage drop conditions in power grid verification

Identifying worst-case voltage drop conditions in every module supplied by the power grid is a crucial problem in modern IC design. In this paper we develop a novel methodology for power grid verification which is based on accurately constructing the space of current variations of the supplied modules and locating its precise points that yield the worst-case voltage drop conditions. The construction of the current space is performed via plain simulation and statistical extrapolation using results from extreme value theory. The method overcomes limitations of past methods which either relied on loosely bounding the worst-case voltage drop, or abstracted the current space in a vague and incomplete set of bound-type constraints. Experimental results verify the potential of the proposed method to identify worst-case conditions and demonstrate the pessimism inherent in previous bound-type approaches

Fast transform-based preconditioners for large-scale power grid analysis on massively parallel architectures

Efficient analysis of massive on-chip power delivery networks is among the most challenging problems facing the EDA industry today. In this paper, we present a new preconditioned iterative method for fast DC and transient simulation of large-scale power grids found in contemporary nanometer-scale ICs. The emphasis is placed on the preconditioner which reduces the number of iterations by a factor of 5X for a 2.6M-node industrial design and by 72.6X for a 6.2M-node synthetic benchmark, compared with incomplete factorization preconditioners. Moreover, owing to the preconditioners special structure that allows utilizing a Fast Transform solver, the preconditioning system can be solved in a near-optimal number of operations, while it is extremely amenable to parallel computation on massively parallel architectures like graphics processing units (GPUs). Experimental results demonstrate that our method achieves a speed-up of 214.3X and 138.7X for a 2.6M-node industrial design, and a speed-up of 1610.5X and 438X for a 3.1M-node synthetic design, over state-of-the-art direct and iterative solvers respectively when GPUs are utilized. At the same time, its matrix-less formulation allows for reducing the memory footprint by up to 33% compared to the memory requirements of the best available iterative solver.

A macromodel technique for VLSI dynamic simulation by mapping pre-characterized transitions

Accurate simulation of digital circuits is an essential part of the design process. High precision models are generally used to confirm logic behavior and estimate power dissipation, which has become an extremely important design parameter. Unfortunately high precision analysis is expensive in computer execution time, and there is always a trade-off between accuracy and speed. This work proposes a new circuit simulation approach by storing a set of pre-characterized transition configurations for each standard library cell in a lookup table. The lookup table contains information about the voltage and the current transient waveform produced by SPICE simulation. The method achieves good accuracy levels for yielding the total or partial current waveform of a circuit in significantly less time compared to SPICE or other commercial tools.

Voltage-drop-constrained optimization of power distribution network based on reliable maximum current estimates

The problem of optimum design of tree-shaped power distribution networks with respect to the voltage drop effect is addressed in this paper. An approach for the width adjustment of the power lines supplying the circuits major functional blocks is formulated, so that the network occupies the minimum possible area under specific voltage drop constraints at all blocks. The optimization approach is based on precise maximum current estimates derived by statistical means from recent advances in the field of extreme value theory. Experimental tests include the design of power grid for a choice of different topologies and voltage drop tolerances in a typical benchmark circuit.

Characterization of the worst-case current waveform excitations in general RLC-model power grid analysis

Validating the robustness of power distribution in modern IC design is a crucial but very difficult problem, due to the vast number of possible working modes and the high operating frequencies which necessitate the modeling of power grid as a general RLC network. In this paper we provide a characterization of the worst-case current waveform excitations that produce the maximum voltage drop among all possible working modes of the IC. In addition, we give a practical methodology to estimate these worst-case excitations on the basis of a sample of the excitation space acquired via plain circuit simulation. In the course of characterizing the worst-case excitations we also establish that the voltage drop function for RLC grid models has nonnegative coefficients, which has been an open problem so far.

Adaptive digital fuzzy hardware in application-specific integrated circuits

This paper presents a generic fuzzy logic system implementation in digital hardware. The architecture developed is oriented to Application-Specific Integrated Circuits (ASICs) and was therefore embedded within an ASIC for a simple control application. Furthermore, a distributed adaptation scheme is proposed for real-time environments. Performance/area tradeoffs for VLSI implementation are discussed.

A parallel fast transform-based preconditioning approach for electrical-thermal co-simulation of power delivery networks

Efficient analysis of massive on-chip power delivery networks is among the most challenging problems facing the EDA industry today. Due to Joule heating effect and the temperature dependence of resistivity, temperature is one of the most important factors that affect IR drop and must be taken into account in power grid analysis. However, the sheer size of modern power delivery networks (comprising several thousands or millions of nodes) usually forces designers to neglect thermal effects during IR drop analysis in order to simplify and accelerate simulation. As a result, the absence of accurate estimates of Joule heating effect on IR drop analysis introduces significant uncertainty in the evaluation of circuit functionality. This work presents a new approach for fast electrical-thermal co-simulation of large-scale power grids found in contemporary nanometer-scale ICs. A state-of-the-art iterative method is combined with an efficient and extremely parallel preconditioning mechanism, which enables harnessing the computational resources of massively parallel architectures, such as graphics processing units (GPUs). Experimental results demonstrate that the proposed method achieves a speedup of 66.1X for a 3.1M-node design over a state-of-the-art direct method and a speedup of 22.2X for a 20.9M-node design over a state-of-the-art iterative method when GPUs are utilized.

A Design Flow for the Precise Identification of the Worst-Case Voltage Drop in Power Grid Analyses

Modern IC designs contain hundreds of millions of transistors and new approaches of multicore chips take place in commercial products. Identifying worst-case voltage drop conditions in every hierarchical module supplied by the power grid is a crucial reliability problem in modern IC design. In this paper we focused our efforts on a complete design flow using innovative results of our recent research work. This approach demonstrates a new implementation of construction of the current space which is performed via plain simulation and statistical extrapolation using results from extreme value theory. Experimental results verify the potential of the estimation engine using industrial EDA tools and perform power grid verification using a custom hierarchical design.

A power grid analysis and verification tool based on a Statistical Prediction Engine

Voltage drops are one of the most stringent problems in modern IC implementation, which is exacerbated by the ever decreasing transistor sizes and interconnect line widths. In order to find the true worst case voltage drop that a power net of a design might suffer, the designer would have to check the voltage drops that occur from the simulation of all possible input vector pairs of a design. This is a prohibitive amount of simulations for modern ICs that have hundreds of inputs. Consequently, designers face two basic challenges, fast and accurate estimation of worst case voltage-drop and accurate modeling of the power distribution network. In this paper we present a voltage-drop aware tool for power grid analysis and verification based on a statistical engine, which can estimate the true worst case voltage drops on a design with a typical confidence level of 99%. The statistical engine is based on extensions to the Extreme Value Theory (EVT) which is a pertinent field of statistics for the estimation of the unknown maximum of a related population from one (or more) of its samples. The paper shows how the statistical engine can take input from gate-level simulation of digital logic, combined with transient simulation of the power and ground network with inductance-aware (RLCK) models. Using these techniques, a designer can estimate the true worst case voltage drop on each and every contact of the power and ground distribution network of a digital design, using a relatively small amount of input vectors, thus greatly reducing the turnaround time for power integrity verification.