Nety M. Krishna

Adhesion and debonding of multi-layer thin film structures

Abstract A fracture mechanics technique to quantitatively measure the adhesion or interfacial fracture resistance of interfaces in thin film structures is described. Adhesion values obtained for the technologically important SiO2/TiN interface in microelectronic interconnect structures are related to a range of material, mechanical and design parameters which include interface morphology and adjacent ductile layer thickness. In addition, the interface was shown to be susceptible to environmentally-assisted subcritical debonding similar to stress corrosion cracking of SiO2 glass in moist air environments. Subcritical debonding behavior was sensitive to a range of material and design parameters, and is expected to have important implications for long term device reliability.

Adhesion and reliability of copper interconnects with Ta and TaN barrier layers

With the advent of copper metallization in interconnect structures, new barrier layers are required to prevent copper diffusion into adjacent dielectrics and the underlying silicon. The barrier must also provide adequate adhesion to both the dielectric and copper. While Ta and TaN barrier layers have been incorporated for these purposes in copper metallization schemes, little quantitative data exist on their adhesive properties. In this study, the critical interface fracture energy and the subcritical debonding behavior of ion-metal-plasma sputtered Ta and TaN barrier layers in Cu interconnect structures were investigated. Specifically, the effects of interfacial chemistry, Cu layer thickness, and oxide type were examined. Behavior is rationalized in terms of relevant reactions at the barrier/dielectric interface and plasticity in adjacent metal layers. (c) 2000 Materials Research Society.

Metal Nanocrystal Memory With Pt Single- and Dual-Layer NC With Low-Leakage

In this letter, we report metal nanocrystal (NC)-based flash memory devices with single-layer (SL) and dual-layer (DL) Pt NCs as the storage element. The devices are fabricated using CMOS compatible process flow with optimized low-leakage high-k Al2O3 as the control dielectric. Large memory window (10 V for SL and 15 V for DL devices) is observed due to overerase, which increases the overall window. Improvement in DL memory window is found to be due to 1.5 times improvement in total stored charge over SL. Excellent high-temperature precycling retention is observed both for SL and DL devices.

\hbox{Al}_{2}\hbox{O}_{3}

The performance and reliability of charge trap flash with single and bi-layer Si-rich and N-rich nitride as the storage node is studied. Single layer devices show lower memory window and poor cycling endurance, and the underlying physical mechanisms for these issues are explained. An engineered trap layer consisting of Si-rich and N-rich nitride interfaced by a SiON barrier layer is proposed. The effect of varying the SiON interfacial layer position on memory window and reliability is investigated. Optimum bi-layer device shows higher memory window and negligible degradation due to cycling (at higher memory window) compared to single layer films. The role of SiON interface in improving the performance and reliability of bi-layer stacks is explained.

Blocking Dielectric

In this paper, we report on the fabrication and reliability characterization of gold (Au) and platinum (Pt) single-layer nanocrystal (NC)-based Flash memory devices for NAND application. The devices are fabricated using a CMOS-compatible process flow with high-quality (low leakage and large breakdown) Al2O3 as the control dielectric. The impact of processing conditions on the NC size, area coverage, and number density is also investigated. Large memory window ( ~ 7.5 V for Au and ~ 10 V for Pt) and good retention are observed for both Au and Pt NC devices. Excellent postcycling retention is also noted for Pt NC devices. Endurance characteristics are found to be of concern as maximum of only 1 times 103 and 4 times 103 cycles can be obtained for Au and Pt devices, respectively. Anneal-temperature-dependent gate leakage is observed in Au devices and is investigated using analytical methods. Diffusion of Au atoms from the NC into the gate dielectrics is seen which correlates to the electrical measurements. Postcycling retention and program/erase of Pt NC devices are shown to be good.

Nitride engineering and the effect of interfaces on Charge Trap Flash performance and reliability

The effect of nitride composition, i.e. Si-rich (Si⁺) and N-rich (N⁺) nitride bi-layers separated by an oxynitride (SiON) layer on memory performance and reliability is studied. Bottom Si⁺ layer and top N⁺ forms the Si⁺/N⁺ bi-layer that is compared to the opposite configuration of N⁺/Si⁺ bi-layer to reveal large impact on memory performance and reliability. Si⁺/N⁺ bi-layers exhibit superior P/E windows and endurance characteristics but worse retention charge loss compared to N⁺/Si⁺ stacks. The oxynitride layer composition and position play a dominant role in trap generation as evident from endurance performance. A low energy-threshold degradation mechanism with higher degradation of the SiON layer with greater H-content is observed. A Si-H bond breaking mechanism is proposed as trap generation mechanism during endurance cycling. Retention is primarily bottom nitride composition dependent as tunnel oxide is shown to be the dominant charge loss path.

Performance and Reliability of Au and Pt Single-Layer Metal Nanocrystal Flash Memory Under nand (FN/FN) Operation

Thin film structures may fail by progressive or time-dependent debonding at stresses far below those required for catastrophic failure. Previous work has shown that progressive debonding in a typical interconnect structure occurs either along the TiN/SiO 2 interface or parallel to this interface in the SiO 2 Such subcritical debonding was found to span several orders of magnitude of debond growth rates and occur at significantly reduced driving forces. The presence of SiO 2 at the failure location indicates that the mechanisms which give rise to stress corrosion cracking in bulk glasses may also play a role in the subcritical debonding behavior of multilayer interconnect structures. Accordingly, this work focuses on the effects of temperature and humidity on subcritical debonding and rationalizes them in terms of the relevant chemical reactions taking place at the debond tip.

The effect of band gap engineering of the nitride storage node on performance and reliability of charge trap flash

Nanocrystal (NC) based memory devices are considered a possible alternative for floating gate (FG) replacement below 30nm node. In this work, endurance reliability of Pt NC devices is investigated for single layer (SL) and dual layer (DL) structures. The degradation in the devices due to Program/Erase (P/E) stress is investigated. Relative improvement in reliability of DL structure over SL structure is shown. A physical model for defect generation in the gate stack is proposed which is able to explain endurance and post-cycling characteristics. Dual layer structure is shown to have better inherent reliability over single layer structure.

Subcritical Debonding of Multilayer Interconnect Structures: Temperature and Humidity Effects

A 3D simulator for metal nanocrystal (NC) flash is developed and verified with published experimental data. The simulator is capable of extracting physical parameters and predicting their impact on cell performance. The simulator is used to optimize cell design and analyze performance with scaling, NC randomness and NC number fluctuations.

Reliability of single and dual Layer Pt nanocrystal devices for NAND flash applications: A 2-region model for endurance defect generation

In this work we investigate the memory performance and reliability of Au nanocrystal memory devices. We analyze the Au NC formation process and fabricate actual test wafers for electrical characterization. With reference to good Pt NC devices, poor performance of Au NC devices is investigated in detail by analytical and electrical methods.