Kaushal K. Singh

Metal Nanocrystal Memory With Pt Single- and Dual-Layer NC With Low-Leakage

In this letter, we report metal nanocrystal (NC)-based flash memory devices with single-layer (SL) and dual-layer (DL) Pt NCs as the storage element. The devices are fabricated using CMOS compatible process flow with optimized low-leakage high-k Al2O3 as the control dielectric. Large memory window (10 V for SL and 15 V for DL devices) is observed due to overerase, which increases the overall window. Improvement in DL memory window is found to be due to 1.5 times improvement in total stored charge over SL. Excellent high-temperature precycling retention is observed both for SL and DL devices.

\hbox{Al}_{2}\hbox{O}_{3}

Photonic crystals (PCs) can be used to trap light in thin-film solar cells to increase optical absorption. We fabricated ultrathin c-Si solar cells whose active layer was patterned into a two-dimensional PC with a square lattice of 450 nm diameter holes spaced at a period of 750 nm. The PC couples incident light into quasiguided modes and can be engineered to increase coupling and thus optimize optical absorption. Both short-circuit current and external quantum efficiency measurements show an enhancement in optical absorption, especially at longer wavelengths. Scanning photocurrent maps confirm the improved optical absorption in the PC regions.

Blocking Dielectric

A precursor, neopentasilane, is used to produce high-quality siliconepitaxy by chemical vapor deposition under 700 ° C with very high growth rates. Low background dopant concentration and excellent crystal quality were determined from secondary-ion-mass spectroscopy and cross sectional transmission electron microscopy. Growth rates as high as 130 nm ∕ min at 600 ° C have been achieved. Growth rates in nitrogen and hydrogen ambients are about equal for neopentasilane, unlike those for growth with low-order silanes. A concerted reaction, where an open site is generated at the same time the adatom is adsorbed, is proposed as a possible mechanism for both the high growth rate with neopentasilane as well as the similar rate with hydrogen and nitrogen carriers.

Ultrathin crystalline-silicon solar cells with embedded photonic crystals

The performance and reliability of charge trap flash with single and bi-layer Si-rich and N-rich nitride as the storage node is studied. Single layer devices show lower memory window and poor cycling endurance, and the underlying physical mechanisms for these issues are explained. An engineered trap layer consisting of Si-rich and N-rich nitride interfaced by a SiON barrier layer is proposed. The effect of varying the SiON interfacial layer position on memory window and reliability is investigated. Optimum bi-layer device shows higher memory window and negligible degradation due to cycling (at higher memory window) compared to single layer films. The role of SiON interface in improving the performance and reliability of bi-layer stacks is explained.

Ultrahigh growth rate of epitaxial silicon by chemical vapor deposition at low temperature with neopentasilane

In this paper, we report on the fabrication and reliability characterization of gold (Au) and platinum (Pt) single-layer nanocrystal (NC)-based Flash memory devices for NAND application. The devices are fabricated using a CMOS-compatible process flow with high-quality (low leakage and large breakdown) Al2O3 as the control dielectric. The impact of processing conditions on the NC size, area coverage, and number density is also investigated. Large memory window ( ~ 7.5 V for Au and ~ 10 V for Pt) and good retention are observed for both Au and Pt NC devices. Excellent postcycling retention is also noted for Pt NC devices. Endurance characteristics are found to be of concern as maximum of only 1 times 103 and 4 times 103 cycles can be obtained for Au and Pt devices, respectively. Anneal-temperature-dependent gate leakage is observed in Au devices and is investigated using analytical methods. Diffusion of Au atoms from the NC into the gate dielectrics is seen which correlates to the electrical measurements. Postcycling retention and program/erase of Pt NC devices are shown to be good.

Nitride engineering and the effect of interfaces on Charge Trap Flash performance and reliability

The effect of nitride composition, i.e. Si-rich (Si⁺) and N-rich (N⁺) nitride bi-layers separated by an oxynitride (SiON) layer on memory performance and reliability is studied. Bottom Si⁺ layer and top N⁺ forms the Si⁺/N⁺ bi-layer that is compared to the opposite configuration of N⁺/Si⁺ bi-layer to reveal large impact on memory performance and reliability. Si⁺/N⁺ bi-layers exhibit superior P/E windows and endurance characteristics but worse retention charge loss compared to N⁺/Si⁺ stacks. The oxynitride layer composition and position play a dominant role in trap generation as evident from endurance performance. A low energy-threshold degradation mechanism with higher degradation of the SiON layer with greater H-content is observed. A Si-H bond breaking mechanism is proposed as trap generation mechanism during endurance cycling. Retention is primarily bottom nitride composition dependent as tunnel oxide is shown to be the dominant charge loss path.

Performance and Reliability of Au and Pt Single-Layer Metal Nanocrystal Flash Memory Under nand (FN/FN) Operation

The novel deposition of GaAs thin films on glass substrates from a solution based route involving the aerosol assisted chemical vapour deposition (AACVD) of As(NMe2)3 and GaMe3 dissolved in toluene is reported. The gallium arsenide films were analysed by scanning electron microscopy (SEM), X-ray powder diffraction (XRD), energy dispersive X-ray (EDX) analysis, X-ray photoelectron spectroscopy (XPS) and Raman spectroscopy. Powder XRD showed that cubic polycrystalline GaAs had been deposited with films grown at the higher temperatures having a Ga to As ratio of 1:1. EDX mapping, XPS depth profiling and SIMS showed that the films contained low levels of contaminants. The method described shows the formation of GaAs films with increasing crystallinity and stoichiometry reaching unity with increasing deposition temperature.

The effect of band gap engineering of the nitride storage node on performance and reliability of charge trap flash

Nanocrystal (NC) based memory devices are considered a possible alternative for floating gate (FG) replacement below 30nm node. In this work, endurance reliability of Pt NC devices is investigated for single layer (SL) and dual layer (DL) structures. The degradation in the devices due to Program/Erase (P/E) stress is investigated. Relative improvement in reliability of DL structure over SL structure is shown. A physical model for defect generation in the gate stack is proposed which is able to explain endurance and post-cycling characteristics. Dual layer structure is shown to have better inherent reliability over single layer structure.

A solution based route to GaAs thin films from As(NMe2)3 and GaMe3 for solar cells

Memory window (MW) and the retention of single-layer (SL) and dual-layer (DL) platinum (Pt) nanocrystal (NC) devices are extensively studied before and after program/erase (P/E) cycling. DL devices show better charge storage capability and reliability over the SL devices. Up to 50% improvement in the stored charge is estimated in the DL device over SL when P/E is performed at equal field. Excellent high temperature and postcycling retention capabilities of SL and DL devices are shown. The impact of the interlayer film (ILF) thickness on the retention of the DL structure is reported. While SL devices show poor P/E cycling endurance, DL cycling is shown to meet the minimum requirements of the multilevel cell (MLC) operation.

Reliability of single and dual Layer Pt nanocrystal devices for NAND flash applications: A 2-region model for endurance defect generation

The growth of epitaxy of silicon–carbon (Si1−yCy) alloy layers on (1 0 0) silicon substrates by chemical vapour deposition (CVD) with a novel precursor, neopentasilane, as the silicon source gas and methylsilane as the carbon source is reported. High quality Si1−yCy alloy layers at growth rates of 18 nm min −1 and 13 nm min −1 for fully substitutional carbon levels of 1.8% and 2.1%, respectively, were achieved. The highest substitutional carbon level achieved was 2.6% (strained perpendicular lattice constant of 5.347 u A) as determined by x-ray diffraction. (Some figures in this article are in colour only in the electronic version)