Neven Orhanovic

Full wave analysis of planar interconnect structures using FDTD-SPICE

This paper describes a full wave approach for analyzing planar interconnect structures, such as power distribution systems in printed circuit boards and multichip modules, using a tightly coupled combination of FDTD and SPICE. The technique enhances the present hybrid full wave circuit methods in terms of robustness and efficiency. The method is applied to a few sample problems to illustrate its accuracy and versatility.

Signal propagation and radiation of single and differential microstrip traces over split image planes

This paper deals with the effect of split power or ground planes on single and differential signals propagating on microstrip structures using the FDTD method. The effect of the split in the image plane on the propagated signals as well as on the radiated fields is examined for different trace separations. The improvement of signal quality and the reduction of the unwanted radiation obtained by running tightly coupled differential traces over the split is examined. The excitation of slot line modes in the split is shown.

Structure decomposition for hybrid analysis of multilayer interconnect systems

A method for decomposing interconnect systems into signal propagation and power distribution parts is presented. The decomposed structure is amenable to hybrid analysis, where each part is analyzed using a separate analysis technique. The decomposition is performed around the discontinuities in the signal propagation paths.

Characterization of microstrip meanders in PCB interconnects

Meandering traces are often used to increase delay times in printed circuit board (PCB) interconnects. An accurate analysis of meanders in todays high speed digital circuits needs to take into account a number of different effects, including near field coupling between the turns of the meander and reflections at the line discontinuities. These effects have a significant impact on the delay and waveshape of the propagated signal. In this paper we analyze microstrip meander structures using a finite difference time domain (FDTD) based full wave method and a quasi-static technique. Signal propagation through meanders with different trace separations is examined. Shortcomings of the quasi-static approach are pointed out. Simple design guidelines are given.

FDTD-SPICE analysis of high-speed cells in silicon integrated circuits

Introduces FDTD-SPICE to the problem of silicon integrated circuit (IC) analysis. The analyzed IC cell is decomposed into active and passive parts. The active part is analyzed using the circuit analysis approach of SPICE while the larger passive on-chip interconnect part is analyzed using the full wave finite difference time domain (FDTD) method. The two methods are coupled in the time domain at the connecting ports. All of the modes propagating on the metal-insulator-semiconductor (MIS) interconnect are taken into account accurately. The advantages of both the circuit and the full wave analysis approaches are retained while avoiding inaccuracies associated with the use of transforms or inverse transforms. The analysis procedure is illustrated on a few small IC cell layout examples.

Return path analyzer based on PEEC and sectioning methods

Return path analysis is very useful in predicting radiation and current distribution from planar structures such as PCBs, MCMs and packages. However, it is very computation intensive and requires millions of meshes in reference planes. Special PEEC based techniques have been used to calculate frequency dependent current distributions in these planes, which may have arbitrary shape. However, this required uniform meshing. A more general method based on fast multipole and variable mesh sizes is used here to considerably speed up the process. In special cases, portions of the structure can be analyzed independently making parallel processing a practical solution to enhance speed. With all these enhancements, it is possible to analyze a complex whole board.

FDTD/spl I.bar/SPICE analysis of EMI and SSO of LSI ICs using a full chip macro model

A method of macro modeling the power and ground circuits of an LSI IC taking into account internal gates has been proposed. Major contributors to simultaneous switching output noise (SSO) and electromagnetic interference (EMI) are the power and ground currents of clock circuits in internal gates which are modeled using simple flip-flop circuits by summing their gate widths and interconnection capacitances. Using such a macro model, methods for reducing SSO and EMI for such LSI chips are analyzed by FDTD/spl I.bar/SPICE. It is shown that the major contributor to SSO and EMI is not I/O circuitry but internal gates. The most effective way to reduce such noise is to implement large decoupling capacitors into a chip.

Compact 2D FDFD based full wave method for the extraction of RLGC parameters of general guided wave structures

A 2D full wave method for computing the frequency dependent RLGC parameters of general dispersive, dissipative guided wave structures is proposed. The method directly computes the modal fields and the complex propagation constant of the structure. The characterization of a mode in the form of its equivalent RLGC parameters makes the method particularly convenient for SPICE modeling. The method is based on the solution of a set of discretized Maxwells equations formulated as a sparse complex general eigenvalue problem.

Chip complexity requires signal and power integrity

With an increase in operating frequency and the complexity of system on a chip (SOC), it becomes important to consider the noise generated along the signal and power/ground interconnections that leads to malfunction. We have developed a new simulation method for the full chip-level signal and power-integrity analysis. The CAD layout data is converted into SPICE transmission line models considering silicon substrate effects. To remove the limitation of size and complexity of layout data in the real LSI chips, a sectioning method using MOR with super linear solver has been introduced. The proposed method can also be extended to the computation of current/voltage distributions leading to EMI analysis

SI and EMI analysis of analog circuit board combination of PEEC and MOR

A method for analyzing SI and EMI of an analog circuit board considering the effect of analog patterns has been proposed. This method uses the combination of PEEC (partial element equivalent circuit) and MOR (model order reduction). Major contributors to signal, power and EMI noise in high power supply circuits are the parasitics of arbitrary shape conductor patterns between discrete components such as power MOS transistors and passive components. The conductor patterns are modeled as meshed RLGC network circuits, and then compressed into a compact circuit model. Voltage and current waveforms in the time domain and EMI in the frequency domain are simulated by using the obtained macro model and nonlinear devices.