Nguyen Dang Chien

Sub-10-nm Tunnel Field-Effect Transistor With Graded Si/Ge Heterojunction

This study presents a new sub-10-nm tunnel field-effect transistor (TFET) with bandgap engineering using a graded Si/Ge heterojunction. Both the height and width of the tunneling barrier are highly controlled by applying gate voltages to ensure a near ideal sub-5-mV/dec switching of scaled sub-10-nm TFETs at 300 K. This study performed a 2-D simulation to elucidate p-body graded Si/Ge heterojunction TFET devices from 50 to 5 nm. The on-state tunneling barrier around the source was narrowed and lowered to demonstrate a high on-current; simultaneously, the off-state tunneling barrier was raised and extended into the drain to control the short-channel effect and ambipolar leakage current. The shorter the length is, the more abrupt is the switching. The breakthrough in subthreshold swing and short-channel effect make the graded Si/Ge TFET highly promising as an ideal green transistor into sub-10-nm regimes.

Schottky Barrier Silicon Nanowire SONOS Memory With Ultralow Programming and Erasing Voltages

A new Schottky barrier (SB) nonvolatile nanowire memory is reported experimentally with efficient low-voltage programming and erasing. By applying an SB source/drain to enhance the electrical field in the silicon gate-all-around nanowire, the nonvolatile silicon-oxide-nitride-oxide-silicon (SONOS) memory can operate at gate voltages of 5 to 7 V for programming and -7 to -9 V for erasing through Fowler-Nordheim tunneling. The larger the gate voltage is, the faster the programming/erasing speed and the wider the threshold-voltage shift are attained. Importantly, the SB nanowire SONOS cells exhibit superior 100-K cycling endurance and high-temperature retention without any damages from metallic silicidation process or field-enhanced tunneling.

A Source-Side Injection Lucky Electron Model for Schottky Barrier Metal–Oxide–Semiconductor Devices

This letter explores source-side injection in Schottky barrier metal-oxide-semiconductor (MOS) devices. Unlike drain-side injection in conventional MOS devices, a source-side lucky electron model predicts the specific source-side injection in Schottky barrier MOS devices. The source-side electric field is derived from the solutions of 2-D Poissons equations. The conformal-mapping method is used to estimate the gate electrode contribution to determine the source-side injected probability. 2-D device simulations confirm the agreements between the analytical models and the numerical results. This study provides a physical understanding of enhanced source-side injection in new Schottky barrier nonvolatile memory.

Design and Modeling of Line-Tunneling Field-Effect Transistors Using Low-Bandgap Semiconductors

The low-bandgap engineering and line-tunneling architecture are the two major techniques to resolve the ON-current issues of tunnel field-effect transistors (TFETs). This paper elucidates the design and modeling of line-tunneling TFETs using low-bandgap materials. Three semiconductors, Ge, InAs, and InSb, are considered as examples to explore their physical operations and analytical models. 2-D device simulations were performed to examine the on/off characteristics. The appropriate operational voltages depend on the associated bandgap of semiconductors. The gate voltage should be larger than the bandgap voltage (Eg/q) to ensure high ON-currents, whereas the drain voltage must be less than the bandgap voltage to control OFF-leakages. Because the minimum tunnel path has a key function in determining the tunneling in line-tunneling TFETs, the tunneling current is reformulated in terms of the minimum tunnel path with friendly compact forms. Two prime design factors, the source concentration and gate-insulator thickness, are examined both analytically and numerically, showing the minimum tunnel path can serve as a useful indicator for low-bandgap line-tunneling TFETs.

Proper determination of tunnel model parameters for indirect band-to-band tunneling in compressively strained Si 1−x Ge x TFETs

Tunnel field-effect transistor (TFET) has served as one of the most attractive candidates for use in future low-power integrated circuits. To explore the current-voltage characteristics of TFET devices, the Kanes tunnel model has been widely used in numerical simulations and physical models to predict the tunneling current produced in the TFETs. This study examines the proper calculations of Kanes model parameters appropriate for the indirect band-to-band tunneling generated in compressively strained Si1-xGex channel on Si-substrate. The calculated parameters were verified with the measured results from experimental TFETs. Good agreements are confirmed between the numerical and measured data without any fitting factors.

Quantum confinement effect in strained-Si 1−x Ge x double-gate tunnel field-effect transistors

The energy bandgap is a key factor to determine the tunneling current in tunnel field-effect transistors (TFETs). This paper numerically investigates the effect of quantum confinement in the double-gate TFETs by evaluating the effective energy-band bandgap of the ultra-thin strained-Si_1-xGe_x body. The band-offset caused by the quantum confinement effect is rapidly increased with increasing the Ge mole fraction because the body thickness must be decreased to retain the same compressive strain of Si_1-xGe_x. A medium Ge more fraction of strained-Si_1-xGe_x is favorable to optimize the device performance in the strained-Si_1-xGe_x double-gate TFETs.

Fringing field and short channel effects in thin-body SOI MOSFETs with shallow source/drain

This work explores numerically the short-channel effects in thin-body SOI MOSFETs with shallow source/drain architecture, where the junction depths are less than the associated silicon body thicknesses. Unique fringing field and short-channel behavior are observed in the unconventional SOI devices. Numerical results of the short-channel effects are compared with those in the conventional SOI MOSFETs. For given silicon body thicknesses, the shallow junction SOI devices exhibit the superior short-channel immunity over the conventional counterparts.

Dependence of Short-Channel Effects on Semiconductor Bandgap in Tunnel Field-Effect Transistors

Scaling down the bandgap is considered as an essential approach to enhance the performance of tunnel field-effect transistors (TFETs). Using two-dimensional simulations, this study examines the dependence of short-channel effects on the semiconductor bandgap in TFETs. It is shown that the short-channel effect is more severe with using lower bandgap materials although the supply voltage is scaled in parallel with the bandgap. For a given bandgap material, the short-channel effect can be well evaluated by the increase of drain-induced barrier thinning (DIBT) with decreasing the channel length. For different bandgap TFETs, however, their short-channel effects cannot be compared properly by comparing the DIBTs. Adequately considering the effect of bandgap on the TFET scalability is necessary in designing scaled integrated circuits.

Roles of Gate-Oxide Thickness Reduction in Scaling Bulk and Thin-Body Tunnel Field-Effect Transistors

Tunnel field-effect transistor (TFET) has recently been considered as a promising candidate for low-power integrated circuits. In this paper, we present an adequate examination on the roles of gate-oxide thickness reduction in scaling bulk and thin-body TFETs. It is shown that the short-channel performance of TFETs has to be characterized by both the off-current and the subthreshold swing because their physical origins are completely different. The reduction of gate-oxide thickness plays an important role in maintaining low subthreshold swing whereas it shows a less role in suppressing off-state leakage in short-channel TFETs with bulk and thin-body structures. When scaling the gate-oxide thickness, the short-channel effect is suppressed more effectively in thin-body TFETs than in bulk devices. Clearly understanding the roles of scaling gate-oxide thickness is necessary in designing advanced scaled TFET devices.

Different scalabilities of N- and P-type tunnel field-effect transistors with Si/SiGe heterojunctions

The dimensional scaling of tunnel field-effect transistors (TFETs) is an indispensable issue to make them competitive with traditional metal-oxide-semiconductor field-effect transistors (MOSFETs). This paper elucidates the scalabilities of very potential TFETs utilizing Si/SiGe heterojunctions operated in n- and p-type operation modes. Although using the Si/SiGe heterostructures helps to improve the on-currents of both n- and p-type TFETs, its assistance in scaling the device dimension is essentially different between the n- and p-type modes. The asymmetric band-offset of Si/SiGe heterojunctions associated with the asymmetric properties of tunneling in n- and p-type TFETs are responsible for the scalability difference. With a high scalability down to sub-10 nm, the graded Si/SiGe heterojunction p-type TFET exhibits a feasible candidate for low-power and highly-scaled integrated circuits.