Chun-Hsing Shih

Physical operation and device design of short-channel tunnel field-effect transistors with graded silicon-germanium heterojunctions

Using graded silicon-germanium heterojunctions, the green tunnel field-effect transistor (TFET) can be scaled down into sub-10 nm regimes without short-channel effects. This work elucidates numerically the physical operation and device design of extremely short-channel TFETs with graded silicon-germanium heterojunctions for future low-power and high-performance applications. Critical device factors, such as the drain profile and bandgap engineering, were examined to generate favorable characteristics in the on-current, on-off switching, and off-leakage of very short TFETs. A mildly doped drain with a pure Ge source is preferred in designing the graded TFETs to optimize a desirable green transistor for low-power integrated circuits.

Nonvolatile Schottky Barrier Multibit Cell With Source-Side Injected Programming and Reverse Drain-Side Hole Erasing

This paper presents a novel Schottky barrier multibit cell with source-side injected programming and reverse drain-side hole erasing. Based on the unique ambipolar conduction of Schottky barrier devices, the source Schottky barrier promotes the amounts of hot electrons at a positive gate voltage to perform source-side injected programming, whereas the drain Schottky barrier enhances the generations of hot holes at a negative gate voltage to carry out reverse drain-side erasing. The proposed Schottky barrier charge-trapping cells are numerically demonstrated to exhibit low-voltage and high-efficiency programming/erasing without the presence of any gate versus source/drain bias tradeoff. The tight and matched distributions of injected carriers make this Schottky barrier cell excellent in future multibit-cell applications.

Multilevel Schottky Barrier Nanowire SONOS Memory With Ambipolar n- and p-Channel Cells

A novel multilevel Schottky barrier nonvolatile nanowire memory is experimentally reported with low-voltage operations and excellent reliability. Using efficient hot-electrons and hot-holes generation associated with Schottky barrier source/drain, the multilevel schemes of silicon nanowire silicon-oxide-nitride-oxide-silicon (SONOS) cells are achieved at adequately low gate voltages. The n-channel cells work at a small gate voltage of 5 to 7 V using multilevel electron programming, whereas the p-channel cells operate at a low gate voltage of -7 to -11 V using multilevel hole programming. The roles of electron and hole carriers in the n-channel cells are exchanged in the p-channel nanowire cells because of ambipolar conduction. Both the n- and p-channel multilevel Schottky barrier nanowire SONOS cells preserve excellent thermal retention and cycling endurance for use in practical embedded and stand-alone nonvolatile memories.

Physical properties and analytical models of band-to-band tunneling in low-bandgap semiconductors

Low-bandgap semiconductors, such as InAs and InSb, are widely considered to be ideal for use in tunnel field-effect transistors to ensure sufficient on-current boosting at low voltages. This work elucidates the physical and mathematical considerations of applying conventional band-to-band tunneling models in low-bandgap semiconductors, and presents a new analytical alternative for practical use. The high-bandgap tunneling generates most at maximum field region with shortest tunnel path, whereas the low-bandgap generations occur dispersedly because of narrow tunnel barrier. The local electrical field associated with tunneling-electron numbers dominates in low-bandgap materials. This work proposes decoupled electric-field terms in the pre-exponential factor and exponential function of generation-rate expressions. Without fitting, the analytical results and approximated forms exhibit great agreements with the sophisticated forms both in high- and low-bandgap semiconductors. Neither nonlocal nor local field is appropriate to be used in numerical simulations for predicting the tunneling generations in a variety of low- and high-bandgap semiconductors.

Design and Modeling of Line-Tunneling Field-Effect Transistors Using Low-Bandgap Semiconductors

The low-bandgap engineering and line-tunneling architecture are the two major techniques to resolve the ON-current issues of tunnel field-effect transistors (TFETs). This paper elucidates the design and modeling of line-tunneling TFETs using low-bandgap materials. Three semiconductors, Ge, InAs, and InSb, are considered as examples to explore their physical operations and analytical models. 2-D device simulations were performed to examine the on/off characteristics. The appropriate operational voltages depend on the associated bandgap of semiconductors. The gate voltage should be larger than the bandgap voltage (Eg/q) to ensure high ON-currents, whereas the drain voltage must be less than the bandgap voltage to control OFF-leakages. Because the minimum tunnel path has a key function in determining the tunneling in line-tunneling TFETs, the tunneling current is reformulated in terms of the minimum tunnel path with friendly compact forms. Two prime design factors, the source concentration and gate-insulator thickness, are examined both analytically and numerically, showing the minimum tunnel path can serve as a useful indicator for low-bandgap line-tunneling TFETs.

Sub-10-nm Asymmetric Junctionless Tunnel Field-Effect Transistors

This study presents a new asymmetric junctionless tunnel field-effect transistor (AJ-TFET) to scale TFETs into sub-10-nm regimes. The asymmetric junctionless p+ source/body and junctional n/p+ drain/body separately optimize the lateral source and drain coupling to efficiently switch the TFETs, producing an abrupt on-off switching. Because of n-drain/p+body junction, the off-state tunnel barrier can be extended into the drain, ensuring an excellent short-channel effect without the limitation of channel lengths. Si/Ge heterojunctions and high-k gate insulators are combined with the AJ-TFETs for additional on-current boosting. Using compact structures and feasible parameters from practical Si-based CMOS technologies, the advancement in the on-off switching and short-channel effect make the AJ-TFET highly promising as an ideal approach into the sub-10-nm regimes.

Proper determination of tunnel model parameters for indirect band-to-band tunneling in compressively strained Si 1−x Ge x TFETs

Tunnel field-effect transistor (TFET) has served as one of the most attractive candidates for use in future low-power integrated circuits. To explore the current-voltage characteristics of TFET devices, the Kanes tunnel model has been widely used in numerical simulations and physical models to predict the tunneling current produced in the TFETs. This study examines the proper calculations of Kanes model parameters appropriate for the indirect band-to-band tunneling generated in compressively strained Si1-xGex channel on Si-substrate. The calculated parameters were verified with the measured results from experimental TFETs. Good agreements are confirmed between the numerical and measured data without any fitting factors.

Reading Operation and Cell Scalability of Nonvolatile Schottky barrier Multibit Charge-Trapping Memory Cells

Using unique ambipolar conduction, a Schottky barrier multibit cell can be programmed using source-side electron injection and can be erased reversely using drain-side hole compensation. This paper numerically discusses the particular reading operation and cell scalability of the Schottky barrier multibit cell resulting from the presence of Schottky source/drain barriers. Forward and reverse reading schemes were examined to determine the multibit-cell state. Critical cell factors, such as channel length, Schottky barrier height, and electrode voltage, were examined to select appropriate structural parameters and operational conditions. Because of the unique Schottky source/drain barriers, the scaled Schottky barrier cell exhibits excellent short-channel immunity and retains the nature of cell reading, source-side programming, and drain-side erasing in a nanoscale regime. Preserving a compact stack-gate architecture and a thorough CMOS process, the Schottky barrier multibit cell serves as a promising candidate for use in nonvolatile embedded and commodity memory devices.

Quantum confinement effect in strained-Si 1−x Ge x double-gate tunnel field-effect transistors

The energy bandgap is a key factor to determine the tunneling current in tunnel field-effect transistors (TFETs). This paper numerically investigates the effect of quantum confinement in the double-gate TFETs by evaluating the effective energy-band bandgap of the ultra-thin strained-Si_1-xGe_x body. The band-offset caused by the quantum confinement effect is rapidly increased with increasing the Ge mole fraction because the body thickness must be decreased to retain the same compressive strain of Si_1-xGe_x. A medium Ge more fraction of strained-Si_1-xGe_x is favorable to optimize the device performance in the strained-Si_1-xGe_x double-gate TFETs.

Dopant segregated Schottky barrier nanowire transistors using low-temperature microwave annealed ytterbium silicide

Thermal budget is one of the major concerns to fabricate three-dimensional (3D) transistors using practical CMOS technologies. In this work, low-temperature microwave annealing is utilized for the fabrication of dopant segregated Schottky barrier gate-all-around nanowire transistors. Low electron Schottky barrier of ytterbium silicide was combined with Phosphorus segregation to form metallic source/drain for high-performance N-channel nanowire transistors. Effects of microwave annealing on metal silicidation as well as dopants segregation are intensively examined by comparing with those using rapid thermal annealing. The minimum microwave power of 200% and processing time of 200 s can be used during annealing to minimize the thermal energy while retaining sufficient activation and silicidation. Experimental results show that the microwave annealing produce better electrical characteristics of dopant segregated Schottky barrier nanowire transistors, serving as a promising approach to fabricate metallic source/drain nanowire transistors for future 3D integration of CMOS technologies.