Nicholas Julian Richardson

Bus interface unit having dual purpose transaction buffer

Apparatus and method of using fully configurable memory, multi-stage pipeline logic and an embedded processor to implement multi-bit trie algorithmic network search engine

PIPELINED NON-BLOCKING LEVEL TWO CACHE SYSTEM WITH INHERENT TRANSACTION COLLISION-AVOIDANCE

Apparatus and method using hashing for efficiently implementing an IP lookup solution in hardware

Method for increasing average storage capacity in a bit-mapped tree-based storage engine by using remappable prefix representations and a run-length encoding scheme that defines multi-length fields to compactly store IP prefixes

Method for increasing storage capacity in a multi-bit trie-based hardware storage engine by compressing the representation of single-length prefixes

Method and system for providing cascaded trie-based network packet search engines

Computer system having non-blocking cache and pipelined bus interface unit

Processor cache system with parity protection and method of operation

System and method for path compression optimization in a pipelined hardware bitmapped multi-bit trie algorithmic network search engine