Nicky Chau-Chun Lu

Effects of grain-boundary trapping-state energy distribution on the activation energy of resistivity of polycrystalline-silicon films

The trapping model assuming a δ-function energy distribution of trapping states has been accepted as an effective first-order approximation for modeling the electrical properties of polysilicon films. However, it predicts that as the doping concentration N is smaller than a critical level N∗, the activation energy of resistivity Ea is independent of N. This is inconsistent with experimental observations. In this paper a trapping model using a Gaussian energy distribution of trapping states is introduced to calculate Ea vs N. The results demonstrate a good agreement with the experimental data of boron-doped polysilicon films. The physical bases of such an improvement and the existence of a Gaussian energy distribution of trapping states have been addressed.

I–V characteristics of polysilicon resistors at high electric field and the non-uniform conduction mechanism

Abstract The non-linear I–V characteristics of polysilicon resistors at high electric fields have been extensively studied. I–V measurements over a temperature range from −194 to 144°C were made on resistors fabricated in polysilicon films deposited by either LPCVD or APCVD with boron, phosphorus or arsenic as dopants having concentration in the range from 1 × 1016 to 5 × 1019 cm−3. As doping level decreases below a critical doping concentration N∗, I–V curves deviate asymmetrically from a hyperbolicsine function. The number of grains ζNg along the effective conduction path versus doping levels shows downward concavity with its maximum value near N ∗ . ζNg is also a function of measurement temperature. It is shown that such anomalous conduction phenomena cannot be explained by previous uniform grain-size models. This paper presents a non-uniform conduction model which effectively describes the high-field conduction behavior of polysilicon resistors and shows that the non-uniform polycrystalline structure has significant effects on the non-linear I–V characteristics.

CURRENT TRANSPORT ACROSS A GRAIN-BOUNDARY IN POLYCRYSTALLINE SEMICONDUCTORS

Abstract A unified approach to current transport across a grain boundary in polycrystalline semiconductors is developed. The resulting expressions for potential barrier and J-V characteristics are of general validity, in contrast to the many derivations of previous models, each with its own conditions of validity. The study concentrates on the carrier-trapping effect, and the trapping-state density can be monoenergetic, continuous, gaussian, or any reasonable distribution. By solving Possions equation under suitable boundary conditions without the depletion approximation, a single formulation is obtained for potential barriers in two adjacent grains with different sizes and doping levels. The grain-boundary scattering effect is approximated as a rectangular potential barrier. The voltage division of an applied bias across the junction is determined under the current-continuity conditions. A single expression with suitable computational simplicity is then presented for the J-V characteristics across the many-valley semiconductor/grain-boundary/semiconductor junction. It uses the generalized WKB approximation and Fermi-Dirac statistics, and also considers the ellipsoidal energy surfaces of different valleys. All the thermionic, thermionic-field, and field emissions are included. As a result, the approach is valid for many-balley semiconductor materials over a wide range of temperatures, trapping-state density distributions, doping concentrations, grain sizes, and crystalline orientations.

A computer designed half Gb 16-channel 819Gb/s high-bandwidth and 10ns low-latency DRAM for 3D stacked memory devices using TSVs

Presented is a novel half Gb DRAM device for 3D stacked systems utilizing TSV. It is designed through the use of a new computer-aided design methodology and which realizes 819 Gb/s bandwidth across 16 channels and <;10ns read latency on a 45nm DRAM process. The architecture is based on small subarrays with short WL and BL to realize the low latency and energy efficiency. We also integrated several circuit techniques, including adaptive power to speed-up access time and banks rotation to reduce thermal issues. The proposed device is also estimated in a system simulation that shows that the power efficiency is higher than comparable systems.