Andre Guntoro

High-performance fpga-based floating-point adder with three inputs

In this paper, we present the design and the implementation of an FPGA-based floating-point adder with three inputs. The design is based on a 5-level pipeline stage in order to distribute the critical paths and to maximize the performance. We examine the data dependencies to minimize the number of the pipeline stages and to reduce the resource allocation. Our design is parameterisable in order to cope with different floating-point formats, including the standard IEEE 754 formats and the custom configurations. The proposed design with the single precision, 32-bit floating-point format, can be operated at 143 MHz on Xilinx Virtex2Pro XC2VP30-7.

Influence of circuit nonidealities on switched-capacitor resonators

Two different approaches exist to implement the resonators needed by a switched-capacitor (SC) bandpass modulator. Both methods use a negative feedback loop around two elements. In the first approach, these elements are SC integrators, and, in the other approach, they are implemented with SC delay cells. In this paper, the impact of nonideal circuit behavior, finite opamp gain, finite unity-gain bandwidth, and nonzero input capacitance, on the center frequency and quality factor of these resonators is analyzed and simulated when used at fs/n.

Low-latency VLSI architecture of a 3-input floating-point adder

In this paper, we present the design and the implementation of a 3-input IEEE 754-compliant floating-point adder. 3 level pipeline stages are used in order to distribute the critical paths and to maximize the operating frequency. The design is customizable to support various floating-point formats, including the standard single precision and double precision formats. The proposed design with the single precision, 32-bit floating-point format consumes 97207 mum square area and has an operating frequency of 420 MHz in a 0.18-mum process.

Configurable VLSI architecture of a 3-input floating-point adder

In this paper, we present the design and the implementation of an IEEE 754-compliant floating-point adder with three inputs. The design is based on a 4-level pipeline stage in order to distribute the critical paths and to maximize the performance. We examine the data dependencies to minimize the number of the pipeline stages. The design is customizable to support various floating-point formats, including the standard single precision and double precision formats. The proposed design with the single precision, 32-bit floating-point format consumes 98712 mum square area and has an operating speed of 556 MHz in a 0.18-mum process.

A novel leakage-estimation method for input-vector control

Input-vector control (IVC) can be used to reduce the static power dissipation of circuits or subcircuits that are idle. In actual microprocessors, many functional units are included multiple times and not in use continuously (e.g. multiplier, ALU) dissipating static and dynamic power. As the static power dissipation depends on the actual input state, IVC can be used to apply the optimal input vector (IV) that causes the lowest static power dissipation in case the unit under consideration is idle. In order to find the optimal input vector, time-consuming simulations for all possible input vectors are inappropriate for actual circuits with data-width of more than 32 bit. Statistical approaches only include a subset of all possible input vectors and are able to finish in acceptable time, but may miss the optimal input vector. In this paper, we introduce a method that qualitatively estimates the static power dissipation in a very fast way such that all possible input vectors are taken into account without requiring time-consuming computations. The Method has been validated experimentally using a 90 nm technologies.

Impact of circuit nonidealities on the implementation of switched-capacitor resonators

High-speed bandpass DeltaSigma modulation is desired in applications that require analog-to-digital conversion of narrowband signals centered around intermediate frequencies. Two different approaches exist to implement the resonators needed by a switched-capacitor (SC) bandpass modulator. Both methods use a negative feedback loop around two elements. In the first approach, these elements are SC integrators, and, in the other approach, they are implemented with SC delay cells. In this paper, the impact of nonideal circuit behavior on the center frequency and quality factor of these resonators is analyzed and simulated when used at fs/n. The nonidealities considered are finite operational amplifier gain, finite unity-gain bandwidth, and nonzero input capacitance.

A Flexible Floating-Point Wavelet Processor

In this paper, we propose a floating-point lifting-based wavelet processor that can perform various forward and inverse DWTs. Our architecture is based on processing elements that can perform either prediction or update on a continuous data stream in every two clock cycles. As wavelet transforms are not only used in JPEG2000, their wavelet filters and the corresponding transformations cannot be satisfied by using integer arithmetics.For this purpose, IEEE 754-compliant floating-point arithmetics are used to compute the transformation.We feature a multi-context configuration to select among various DWTs. Different memory sizes and multi-level transformations are supported. For the 32-bit implementation, SNR values between 124-144 dB can be achieved. The estimated area of the proposed wavelet processor with 2×2×512 words memory and 8 PEs configuration in a 0.18-¿m technology is 8.3 mm square and the estimated operating frequency is 351 MHz.

High-performance floating-point VLSI architecture of a lifting-based wavelet processor

In this paper, we propose a high-performance lifting-based wavelet processor that can perform various forward and inverse DWTs. Our architecture is based on NxM PEs which can perform either prediction or update on a continuous data stream in every clock cycle. In order to improve the accuracy, floating-point arithmetics are used to compute the transformation. To cope with different wavelet filters, we feature a multi-context configuration to select among various DWTs. For the 32-bit implementation, the estimated area of the proposed wavelet processor with 2times8 PEs in a 0.18-mum technology is 4.8 mm square and the estimated operating frequency is 308 MHz.

High-performance floating-point VLSI architecture of lifting-based forward and inverse wavelet transforms

In this paper, we propose a high-performance lifting-based wavelet processor that can perform various forward and inverse Discrete Wavelet Transforms (DWTs). Our architecture is based on processing elements which can perform either prediction or update on a continuous data stream in every clock cycle. In order to improve the accuracy, IEEE 754 floating-point arithmetics are used to compute the transformation. We also consider the normalization step which takes place at the end of the forward DWT or at the beginning of the inverse DWT. To cope with different wavelet filters, we feature a multi-context configuration to select among various DWTs. For the 32-bit implementation, the estimated area of the proposed wavelet processor with 8 processing elements and 2 times 256 words memory in a 0.18-mum technology is 2.2 mm2 and the estimated operating frequency is 340 MHz.

Novel approach on lifting-based DWT and IDWT processor with multi-context configuration to support different wavelet filters

In this paper, we propose a lifting-based DWT processor that can perform various forward and inverse transforms. Contrary to other lifting-based processors which focus on JPEG2000, our design is based on the fact that the wavelet transformations are not used only in the area of image processing and wavelet filters may not be represented as integer numbers. The proposed architecture is based on NxM processing elements which require only one multiplier and one adder to perform prediction/update on a continuous data stream. The multi-context feature allows the processor to be configured for different types of transformations in a simple manner.