Nicola Carta

The Multi-Dataflow Composer tool: A runtime reconfigurable HDL platform composer

Dataflow Model of Computation (D-MoC) is particularly suitable to close the gap between hardware architects and software developers. Leveraging on the combination of the D-MoC with a coarse-grained reconfigurable approach to hardware design, we propose a tool, the Multi-Dataflow Composer (MDC) tool, able to improve time-to-market of modern complex multi-purpose systems by allowing the derivation of HDL runtime reconfigurable platforms starting from the D-MoC models of the targeted set of applications. MDC tool has proven to provide a considerable on-chip area saving: the 82% of saving has been reached combining of different applications in the image processing domain, adopting a 90 nm CMOS technology. In future the MDC tool, with a very small integration effort, will also be extremely useful to create multi-standard codec platforms for MPEG RVC applications.

A coarse-grained reconfigurable approach for low-power spike sorting architectures

Spike sorting is a critical task in neural signal decoding because of its computational complexity. From this perspective, the research trend in the last years aimed at designing massively parallel hardware accelerators. However, for implantable system with a reduced number of channels, as could be those interfaced to the Peripheral Nervous Systems (PNS) for neural prostheses, the efficiency in terms of area and power is in contrast with such a parallelism exploitation. In this paper, a novel approach based on high-level dataflow description and automatic hardware generation is presented and evaluated on an on-line spike sorting algorithm for PNS signals. Results in the best case revealed a 71% of area saving compared to more traditional solutions, without any accuracy penalty. With respect to single kernels execution, better latency performance are achievable still minimizing the number of adopted resources.

An HV-CMOS Integrated Circuit for Neural Stimulation in Prosthetic Applications

An integrated neural stimulator for prosthetic applications, realized with a high-voltage CMOS 0.35-μm process, is presented. The device is able to provide biphasic current pulses to stimulate eight electrodes independently. A voltage booster generates a 17-V voltage supply in order to guarantee the programmed stimulation current even in case of high impedances at the electrode-tissue interface. Pulse parameters such as amplitude, frequency, and width can be programmed digitally. The device has been successfully tested by means of both electrical and in vivo tests, and the results show its capability to provide currents on the order of hundreds of microamperes with impedances on the order of tens of kiloohms.

An integrated interface for peripheral neural system recording and stimulation: system design, electrical tests and in-vivo results.

The prototype of an electronic bi-directional interface between the Peripheral Nervous System (PNS) and a neuro-controlled hand prosthesis is presented. The system is composed of 2 integrated circuits: a standard CMOS device for neural recording and a HVCMOS device for neural stimulation. The integrated circuits have been realized in 2 different 0.35μm CMOS processes available from ams. The complete system incorporates 8 channels each including the analog front-end, the A/D conversion, based on a sigma delta architecture and a programmable stimulation module implemented as a 5-bit current DAC; two voltage boosters supply the output stimulation stage with a programmable voltage scalable up to 17V. Successful in-vivo experiments with rats having a TIME electrode implanted in the sciatic nerve were carried out, showing the capability of recording neural signals in the tens of microvolts, with a global noise of 7μVrms, and to selectively elicit the tibial and plantar muscles using different active sites of the electrode.

A Custom MPSoC Architecture With Integrated Power Management for Real-Time Neural Signal Decoding

Bioengineering research is posing hard challenges to digital embedded system designers. Tight real-time constraints, miniaturization, and low power are critical issues exacerbated by applications requiring the implant of electronic devices in the patients body. Among them, neurocontrolled motor prostheses are on the cutting edge of the research in the field, requiring the real-time neural signal decoding to extract the patients movement intention in order to control the mechatronic device. Despite the literature in the field, how to implement a highly-portable and reliable integrated platform is still an open question. In this paper, we propose a field-programmable gate array-based prototype of an multi-processor system-on-chip embedded architecture that implements an online neural signal decoding algorithm. The prototype is capable of respecting the real-time constraints posed by the application when clocked at less than 50 MHz. Considering that the application workload is extremely data dependent and unpredictable, the architecture has to be dimensioned taking into account critical worst-case operating conditions to ensure robustness. To compensate the resulting over-provisioning of the system architecture, a software-controllable power management has been integrated. Experimental results demonstrate the real-time behavior and allow evaluating the usefulness of the proposed power management technique on public databases.

Compact, Multi-Channel, Electronic Interface for PNS Recording and Stimulation

A multi-channel system for neural signal recording/stimulation is presented. The system is split on two devices: an implantable High Voltage (HV) CMOS integrated circuit (IC) hosting a sigma delta modulator, together with a low noise preamplifier/prefilter and a digital platform for sigma delta decimation/control implemented on a FPGA. This innovative approach guarantees a robust communication link while minimizing the blocks to be implanted, saving power and area. The recording unit exhibits an IRN = 2.12μVrms in 800Hz − 8kHz bandwidth, a programmable gain in the range 45.4dB − 58dB and a 14-bit A/D conversion. The IC hosts also a current-mode stimulator able to deliver currents in the range of hundreds of microampere to electrodes with impedances up to 100kΩ.

Impact of threshold computation methods in hardware wavelet denoising implementations for neural signal processing

Wavelet denoising effectiveness has been proven in neural signal processing applications characterized by a low SNR. This non-linear approach is implemented through the application of some thresholds on the detail signals coming from a sub-band decomposition. The computation of the thresholds could exhibit a high latency when involving some estimators such as the Median Absolute Deviation (MAD), which is critical for real-time applications. When a VLSI implementation is pursued for low-power purposes, such as in the neuroprosthetic field, these aspects cannot be overlooked. This paper presents an analysis of the main VLSI hardware implementation figures related to this specific aspect of the signal denoising by wavelet processing. Xilinx System Generator has been exploited as a design and co-simulation tool to ease the hardware development on off-the-shelf FPGA platforms. The MAD estimator has been both combinatorially and sequentially implemented, and compared against the sample standard deviation. The study reveals similar performance on the neural signals but dramatically worse implementation figures for the MAD. The combinatorial version of the MAD actually prevents an efficient implementation on medium-small devices. This result is important to perform a correct implementation choice for implantable real-time systems, where the device size is relevant for an usable realization.

Early Stage Automatic Strategy for Power-Aware Signal Processing Systems Design

Complexity management, portability and long term adaptivity are common challenges in different fields of embedded systems, normally colliding with the needs of efficient resource utilization and power balance. Image/signal processing systems, though required to offer a large variety of complex functions, have also to deal with battery-life limitations. Wearable signal processing systems, for example, should provide high performance and support new generation standards without compromising their portability and their long-term usability. These constraints challenge hardware designers: early stage trade-off analysis and power management automated techniques are helpful to guarantee a reasonable time-to-market. In the field of video codec specifications, the MPEG standard known as Reconfigurable Video Coding (RVC) framework addresses functional complexity and adaptivity leveraging on the intrinsic modularity of the dataflow model of computation, but it still lacks in offering power management support. The main contribution of this work is providing an automatic early-stage power management methodology to be adopted within the MPEG-RVC context. Starting from different high-level specifications, our mapping methodology identifies directly on the high-level models disjointed homogeneous logic clock regions, where the platform resources can be enabled/disabled together without affecting the overall system performance. To extend its usability to the RVC community, we have integrated this methodology within the Multi-Dataflow Composer (MDC) tool. MDC is a tool for on-the-fly reconfigurable signal processing platforms deployment. In this paper, we extended MDC to address power-aware multi-context systems. To prove the effectiveness of our work, a coprocessor for image and video processing acceleration has been assembled. This latter has been synthesized on a 90 nm ASIC technology, where demonstrated up to 90 % of reduction in the dynamic power consumption on different dataflow-intensive applications. The coprocessor has been implemented also on FPGA, confirming, partially, the benefits of adopting the proposed methodology.

VLSI wavelet denoising of neural signals: Critical appraisal of different algorithmic solutions for threshold estimation

Abstract: Wavelet denoising represents a common preprocessing step for several biomedical applications exposing low SNR. When the real-time requirements are joined to the fulfilment of area and power minimization for wearable/implantable applications, such as for neuroprosthetic devices, only custom VLSI implementations can be adopted. In this case, every part of the algorithm should be carefully tuned. The usually overlooked part related to threshold estimation is deeply analysed in this paper, in terms of required hardware resources and functionality, exploiting Xilinx System Generator for the design of the architecture and the co-simulation. The analysis reveals how the widely used Median Absolute Deviation (MAD) could lead to hardware implementations highly inefficient compared to other dispersion estimators demonstrating better scalability, relatively to the specific application.