Nicolas Borrel

Experimental validation of a Bulk Built-In Current Sensor for detecting laser-induced currents

Bulk Built-In Current Sensors (BBICS) were developed to detect the transient bulk currents induced in the bulk of integrated circuits when hit by ionizing particles or pulsed laser. This paper reports the experimental evaluation of a complete BBICS architecture, designed to simultaneously monitor PMOS and NMOS transistors, under Photoelectric Laser Stimulation (PLS). The obtained results are the first experimental proof of the efficiency of BBICS in laser fault injection detection attempts. Furthermore, this paper highlights the importance of BBICS tapping in a sensitive area (logical gates) for improved laser detection. It studies the performances of this BBICS architecture and suggests modifications for its future implementation.

Electrical model of an NMOS body biased structure in triple-well technology under photoelectric laser stimulation

This study is driven by the need to optimize failure analysis methodologies based on laser/silicon interactions with an integrated circuit using a triple-well process. It is therefore mandatory to understand the behavior of elementary devices to laser illumination, in order to model and predict the behavior of more complex circuits. This paper presents measurements of the photoelectric currents induced by a pulsed-laser on an NMOS transistor in triple-well Psubstrate/DeepNwell/Pwell structure dedicated to low power body biasing techniques. This evaluation compares the triple-well structure to a classical Psubstrate-only structure of an NMOS transistor. It reveals the possible activation change of the bipolar transistors. Based on these experimental measurements, an electrical model is proposed that makes it possible to simulate the effects induced by photoelectric laser stimulation.

SEU sensitivity and modeling using pico-second pulsed laser stimulation of a D Flip-Flop in 40 nm CMOS technology

This paper presents the design of a CMOS 40 nm D Flip-Flop cell and reports the laser fault sensitivity mapping both with experiments and simulation results. Theses studies are driven by the need to propose a simulation methodology based on laser/silicon interactions with a complex integrated circuit. In the security field, it is therefore mandatory to understand the behavior of sensitive devices like D Flip-Flops to laser stimulation. In previous works, Roscian et al., Sarafianos et al., Lacruche et al. or Courbon et al. studied the relations between the layout of cells, its different laser-sensitive areas and their associated fault model using laser pulse duration in the nanosecond range. In this paper, we report similar experiments carried out using a shorter laser pulse duration (30 ps instead of 50 ns). We also propose an upgrade of the simulation model they used to take into account laser pulse durations in the picosecond range on a logic gate composed of a large number of transistors for a recent CMOS technology (40 nm).

Electrical model of a PMOS body biased structure in triple-well technology under pulsed photoelectric laser stimulation

This study is driven by the need to optimize failure analysis methodologies based on laser/silicon interactions with an integrated circuit using a triple-well process. It is therefore mandatory to understand the behavior of elementary devices to laser illumination, in order to model and predict the behavior of more complex circuits. This paper presents measurements of the photoelectric currents induced by a pulsed-laser on a PMOS transistor in triple-well Psubstrate/DeepNwell/Pwell structure dedicated to low power body biasing techniques. This evaluation compares the triple-well structure to a classical Psubstrate-only structure of PMOS transistor. It reveals the possible activation of the bipolar transistors. Based on these experimental measurements, an electrical model is proposed that makes it possible to simulate the effects induced by photoelectric laser stimulation.

Electrical model of an Inverter body biased structure in triple well technology under pulsed photoelectric laser stimulation

This study is driven by the need to optimize reliability and failure analysis methodologies based on laser/silicon interactions with an integrated circuit using a triple-well process. Nowadays, single event effect (SEE) evaluations due to radiation impacts are critical in fault tolerance and security field. The prediction of a SEE occurring on electronic devices is proposed by the determination and modeling of the phenomena under pulsed laser stimulation. This paper presents measurements of the photoelectric currents induced by a pulsed-laser on an inverter in a triple-well Psubstrate/DeepNwell/Pwell structure dedicated to low power body biasing techniques. It reveals the possible activation change of the parasitic bipolar transistors. Based on these experimental mea- surements, an electrical model is proposed that makes it possible to simulate the effects induced by photoelectric laser stimulation. Therefore this electrical model could be used as a tool for characterizing more complex CMOS circuits under photoelectrical laser stimulation.

Laser testing of a double-access BBICS architecture with improved SEE detection capabilities

The paper reports the experimental validation of a new Bulk Built-In Current Sensor (BBICS) designed and implemented in a 40nm CMOS technology. The double-access architecture provides improved SEE detection as confirmed by laser experiments.

Dynamic current reduction of CMOS digital circuits through design and process optimization

This paper presents an original solution to decrease significantly the power consumption of CMOS digital circuits. The supply voltage VDD and the MOSFET width are reduced and allow lowering the dynamic current of circuits by 25%. A CAD-to-mask script was developed in order to automatically reduce all physical widths of low-voltage transistors used in standard cells. With this operation, no additional redesign of standard cells was necessary. Moreover, a new optimized process based on e-NVM (embedded Non-Volatile Memory) CMOS 80 nm technology is developed. ION current is improved by 15% and 50% for NMOS and PMOS transistors, respectively. This, let us decrease dynamic current without impacting circuit performance. Finally, the static current of the circuit is reduced by 60% through design and process optimization.

Influence of triple-well technology on laser fault injection and laser sensor efficiency

This study is driven by the need to understand the influence of a Deep-Nwell implant on the sensitivity of integrated circuits to laser-induced fault injections. CMOS technologies can be either dual-well or triple-well. Triple-well technology has several advantages compared to dual-well technology in terms of electrical performances. Single-event responses have been widely studied in dual-well whereas SEE (single event effects) in triple-well is not well understood. This paper presents a comparative analysis of soft error rate and countermeasures sensors with for these two techniques in 40 nm and 90 nm CMOS technology. First, laser fault injection on registers were investigated, showing that triple-well technology is more vulnerable. Similarly, we studied the efficiency of Bulk Built-In Current Sensors (BBICS) in detecting laser induced fault injection attempts for both techniques. This sensor was found less effective in triple-well. Finally, a new BBICS compliant with body-biasing adjustments is proposed in order to improve its detection efficiency.