Franck Julien

Impact of hump effect on MOSFET mismatch in the sub-threshold area for low power analog applications

Analog circuit designs are often biased to work in sub-threshold mode with good gate-source voltage matching performances. Depending on the process, hump effect may change the MOS characteristics for negative Bulk-Source Voltage (VBS) and have a slight impact for VBS=0V. To model the hump effect, two narrow parasitic MOS are introduced in parallel with the main device. To accurately simulate matching degradation in sub-threshold mode, these parasitic transistors, in case of hump effect, have to be considered.

Dynamic power reduction through process and design optimizations on CMOS 80 nm embedded non-volatile memories technology

This paper describes different solutions to decrease dynamic consumption of circuits processed on an embedded non-volatile memories CMOS 80 nm technology. Up to 25 % in dynamic power reduction is demonstrated without degrading performances and static leakages of devices and above all, with full DMR compliancy. Ring oscillator designs are used to estimate the dynamic power gain, comparing new development process (B) to reference process (A) currently in use in manufacturing.

Gate Voltage Matching Investigation for Low-Power Analog Applications

On CMOS technology, some process steps can create a parasitic phenomenon named “hump effect.” This parasitic effect can have a strong impact on gate voltage matching of differential pairs and, as a consequence, on analog circuit performances. In this context, several solutions to limit or remove this hump effect are proposed and described. Silicon data obtained at package and wafer levels for different temperatures are analyzed.

Active “multi-fingers”: Test structure to improve MOSFET matching in sub-threshold area

Low power analog applications are often designed under threshold and can be degraded by hump effect. This effect is explained through device dimensions and body bias studies. A MOSFET matching improvement in sub-threshold area is demonstrated with active “multi-fingers” test structure.

Octagonal MOSFET: Reliable device for low power analog applications

Low power analog circuits needs large and short MOSFETs biased in the sub-threshold area with good performances in terms of matching. In order to reach these specifications, octagonal transistors are proposed. Due to their design, these transistors avoid hump effect. As a consequence, gate-source voltage matching under-threshold is always at its best level. Moreover, the paper shows the device robustness to hot carrier stress is improved on octagonal NMOS; VT matching degradation due to hot carrier stress is also improved with an octagonal design.

Matching degradation of threshold voltage and gate voltage of NMOSFET after Hot Carrier Injection stress

Device degradation modelling is more and more important for reliable circuit design. On MOSFET, the threshold voltage drift in time can lead to circuit performance degradation. In this study, VT shift due to Hot Carrier Injection stress is accelerated on small width devices. VT matching is also degraded during stress as a function of VT deterioration. This width dependence allows explaining gate voltage matching behavior in the sub-threshold area used in low power analog applications.

High voltage MOSFETs integration on advanced CMOS technology: Characterization of thick gate oxides incorporating high k metal gate stack from logic core process

This paper presents the performance and reliability evaluation of high voltage MOS gate stacks integrated in an advanced CMOS technology platform. The aim of this study is to evaluate the compatibility of a thick silicon dioxide with a high-k metal gate stack which replaces the standard polysilicon gate. Using capacitors, physical, electrical, and reliability characterizations are carried out and TiN metal gate is found to be a potential issue as it induces a high density of interfacial traps. Despite these traps, oxide lifetime could still meet demanding requirements. Thus, using the high-k metal gate stack on top of a thick SiO2 gate oxide could be a potential solution for high voltage transistors integration on advanced CMOS platforms with embedded non-volatile memories.

Temperature and hump effect impact on output voltage spread of low power bandgap designed in the sub-threshold area

Analog circuit designs are often biased to work in sub-threshold mode for low power constraints and for better gate-source voltage matching performances. Depending on process, hump effect may change MOS characteristics for negative Bulk-Source Voltage (VBS) and have a slight impact for VBS=0V. Actually, even without body effect, hump mainly degrades MOS matching performances in the sub-threshold area with significant temperature dependence. Thus, in order to accurately simulate bandgap performances, modeling of hump effect has to be considered.

Poly-Silicon gate pre-doping implantation impact on MOSFET matching performances

This paper demonstrates how poly-Silicon gate pre-doping implantation impacts MOS matching performances. Measurements are performed on test structures (MOS pairs / capacitors) and analog circuits, using five different processes with pre-doping implantation energy variation (from 35 to 10 KeV) and tilt variation (7° and 25°). TCAD simulations validate a channel counter-doping due to high pre-doping implantation energy causing mismatch degradation.

Dynamic current reduction of CMOS digital circuits through design and process optimization

This paper presents an original solution to decrease significantly the power consumption of CMOS digital circuits. The supply voltage VDD and the MOSFET width are reduced and allow lowering the dynamic current of circuits by 25%. A CAD-to-mask script was developed in order to automatically reduce all physical widths of low-voltage transistors used in standard cells. With this operation, no additional redesign of standard cells was necessary. Moreover, a new optimized process based on e-NVM (embedded Non-Volatile Memory) CMOS 80 nm technology is developed. ION current is improved by 15% and 50% for NMOS and PMOS transistors, respectively. This, let us decrease dynamic current without impacting circuit performance. Finally, the static current of the circuit is reduced by 60% through design and process optimization.