Nicolas Fournel

Using binary translation in event driven simulation for fast and flexible MPSoC simulation

In this paper, we investigate the use of instruction set simulators (ISS) based on binary translation to accelerate full timed multiprocessor system simulation at transaction level. To have an accurate timing behavior, we had to firstly solve timing issues in processor modeling, secondly define fast and precise cache models, and thirdly solve the synchronization issues due to the different models of computation used in the ISSes and in the rest of the system. We present an integration solution that covers these issues and detail its implementation. We have experimented our proposal using processors models provided by the QEMU framework to replace the existing ISSes and SystemC TLM as simulation environment for the whole platform. This approach proposes a range of solutions trading off simulation speed versus accuracy. The experiments show that even for the most precise configuration, the simulation speedup is still significant.

On MPSoC Software Execution at the Transaction Level

This article presents a wide variety of techniques for realizing transaction-level models of the increasingly large-scale multiprocessor systems on chip. It describes how such models of hardware allow subsequent software integration and system performance evaluation.

Speeding-up SIMD instructions dynamic binary translation in embedded processor simulation

This paper presents a strategy to speed-up the simulation of processors having SIMD extensions using dynamic binary translation. The idea is simple: benefit from the SIMD instructions of the host processor that is running the simulation. The realization is unfortunately not easy, as the nature of all but the simplest SIMD instructions is very different from a manufacturer to an other. To solve this issue, we propose an approach based on a simple 3-addresses intermediate SIMD instruction set on which and from which mapping most existing instructions at translation time is easy. To still support complex instructions, we use a form of threaded code. We detail our generic solution and demonstrate its applicability and effectiveness using a parametrized synthetic benchmark making use of the ARMv7 NEON extensions executed on a Pentium with MMX/SSE extensions.

Dynamic many-process applications on many-tile embedded systems and HPC clusters

In the next decade, a growing number of scientific and industrial applications will require power-efficient systems providing unprecedented computation, memory, and communication resources. A promising paradigm foresees the use of heterogeneous many-tile architectures. The resulting computing systems are complex: they must be protected against several sources of faults and critical events, and application programmers must be provided with programming paradigms, software environments and debugging tools adequate to manage such complexity. The EURETILE (European Reference Tiled Architecture Experiment) consortium conceived, designed, and implemented: 1- an innovative many-tile, many-process dynamic fault-tolerant programming paradigm and software environment, grounded onto a lightweight operating system generated by an automated software synthesis mechanism that takes into account the architecture and application specificities; 2- a many-tile heterogeneous hardware system, equipped with a high-bandwidth, low-latency, point-to-point 3D-toroidal interconnect. The inter-tile interconnect processor is equipped with an experimental mechanism for systemic fault-awareness; 3- a full-system simulation environment, supported by innovative parallel technologies and equipped with debugging facilities. We also designed and coded a set of application benchmarks representative of requirements of future HPC and Embedded Systems, including: 4- a set of dynamic multimedia applications and 5- a large scale simulator of neural activity and synaptic plasticity. The application benchmarks, compiled through the EURETILE software tool-chain, have been efficiently executed on both the many-tile hardware platform and on the software simulator, up to a complexity of a few hundreds of software processes and hardware cores.

EURETILE Design Flow: Dynamic and Fault Tolerant Mapping of Multiple Applications Onto Many-Tile Systems

EURETILE investigates foundational innovations in the design of massively parallel tiled computing systems by introducing a novel parallel programming paradigm and a multi-tile hardware architecture. Each tile includes multiple general-purpose processors, specialized accelerators, and a fault-tolerant distributed network processor, which connects the tile to the inter-tile communication network. This paper focuses on the EURETILE software design flow, which provides a novel programming environment to map multiple dynamic applications onto a many-tile architecture. The elaborated high-level programming model specifies each application as a network of autonomous processes, enabling the automatic generation and optimization of the architecture-specific implementation. Behavioral and architectural dynamism is handled by a hierarchically organized runtime-manager running on top of a lightweight operating system. To evaluate, debug, and profile the generated binaries, a scalable many-tile simulator has been developed. High system dependability is achieved by combining hardware-based fault awareness strategies with software-based fault reactivity strategies. We demonstrate the capability of the design flow to exploit the parallelism of many-tile architectures with various embedded and high performance computing benchmarks targeting the virtual EURETILE platform with up to 192 tiles.

Adaptive Dynamic Voltage and Frequency Scaling Algorithm for Symmetric Multiprocessor Architecture

Symmetric multiprocessor architectures (SMP) are gaining popularity for system on chip (SoC) applications as they provide an interesting power/performance/flexibility tradeoff. We address the problem of power consumption in such architectures by designing a new adaptive Dynamic Voltage Frequency Scaling (DVFS) algorithm for non real time operating system (non-RTOS) running on a SMP-SoC. We show the effectiveness of our algorithm on a cycle accurate simulation environment running a real-life multi-threaded application. The experimental results show a potential gain of up to 55%. I. INTRODUCTION

Transparent and portable agent based task migration for data-flow applications on multi-tiled architectures

Fully distributed memory multi-processors (MPSoC) implemented in multi-tiled architectures are promising solutions to support modern sophisticated applications, however, reliability of such systems is always an issue. As a result, system-level solution like task migration keeps its importance. Transferring the execution of a task from one tile to another helps keep acceptable reliability of such systems. A tile contains at least one processor and associated peripherals with a communication device responsible for inter-tile communications. We propose in this work a task migration technique that targets data-flow applications running on multi-tiled architectures. This technique uses a middleware layer that makes it transparent to application programmers and eases its portability over different multi-tiled architectures. It can be deployed on small operating systems that support neither MMU nor dynamic loading for task code. We show that this technique is operational on x86 based real hardware platform. Experimental results show low overhead both in memory and performance without much variance.

Fast simulation of systems embedding VLIW processors

Virtual prototyping of MPSoCs requires fast processor simulation models. Dynamic binary translation is an efficient technology for instruction set simulation, but as it is basically used for effortless code migration, it targets mostly general purpose processors. As many heterogeneous MPSoCs include VLIW processors, we propose and detail in this paper a strategy to perform dynamic binary translation of VLIW codes on scalar architectures for simulation purposes. Our simulation experiments show that it is a few orders of magnitude faster than direct instruction interpretation, although the translator includes no optimization.

Collecting traces in dynamic binary translation based virtual prototyping platforms

Bugs or inefficiencies appearing in MPSoC platforms can have a very broad range of sources. However, due to the huge number of possible execution interleavings, reproducing the conditions of occurrence of a given error/performance issue is very difficult. One solution to this problem consists of tracing an execution for later analysis. This paper details the challenges and issues behind the production of a well formed trace in a transaction accurate virtual prototyping environment that uses dynamic binary translation as processor simulation technology. We propose a solution which requires modification of the dynamic compilation process, but stays non-intrusive, and demonstrate its feasibility on several examples.

Fast and accurate branch predictor simulation

The complexity of embedded processors has raised dramatically, due to the addition of architectural add-ons which improve performances significantly. High level models used in system simulation usually ignore these additions as the major issue is functional correctness. However, accurate estimates of software execution is sometimes required, therefore we focus in this paper on one of theses architectural features, the branch predictor. Unfortunately, advanced branch predictors use large tables, so that models directly implementing these schemes slow down simulation dramatically. To limit the simulation overhead, we define a modeling approach that we demonstrate on a state of the art predictor. We implemented the model in a dynamic binary translation based instruction set simulator and measured an accuracy of prediction of about 95% for a run-time overhead of less than 5%.