Nicolas Rouger

Series-coupled silicon racetrack resonators and the Vernier effect: theory and measurement

Silicon-on-insulator racetrack resonators can be used as multiplexers in wavelength division multiplexing applications. The free spectral range should be comparable to the span of the C-band so that a maximum number of channels can be multiplexed. However, the free spectral range is inversely proportional to the length of the resonator and, therefore, bending losses can become non-negligible. A viable alternative to increase the free spectral range is to use the Vernier effect. In this work, we present the theory of series-coupled racetrack resonators exhibiting the Vernier effect. We demonstrate the experimental performance of the device using silicon-on-insulator strip waveguides. The extended free spectral range is 36 nm and the interstitial peak suppression is from 9 dB to 17 dB.

Temperature Effects on Silicon-on-Insulator (SOI) Racetrack Resonators: A Coupled Analytic and 2-D Finite Difference Approach

This paper presents a detailed analysis of racetrack resonators on silicon on insulator substrates. Both the temperature effects and the particularities of silicon nanophotonics are considered throughout the approach. This paper provides a detailed description of the numerical modeling and its application to different designs, while providing several charts and fitting equations. The results presented in this paper can be applied to three major applications: Thermo-optical tuning of optical resonators, thermo-optical modulator and wide range/high sensitivity temperature sensors. While quantifying the temperature effects, this paper also provides useful answers on how critical the temperature parameter is in the optical cavity behaviour.

Loss Free Gate Driver Unipolar Power Supply for High Side Power Transistors

The paper presents a simple and cost effective solution to supply high side power electronic switch gate drivers. The solution can be integrated and it is demonstrated that it can be loss free, depending on how the power switch is driven. The solution is based on a pulsed linear regulator, only sensitive to a positive dv/dt. At every main power switchs turn OFF, it recycles the switching losses in order to recharge a storage capacitor. The paper presents the global operation and focuses on interesting and important operating characteristics thanks to simulation and practical results.

High-Efficiency and Fully Integrated Self-Powering Technique for Intelligent Switch-Based Flyback Converters

To answer the low cost and simplicity necessities for massive market converter applications (home appliance and automotive, for example) and with the help of the monolithic integration, new components have been developed by industry. This approach leads to cost and volume reductions. In the case of intelligent power MOSFETs, the control part is supplied through one supplementary winding, integrated with the flyback converters inductor. The result is an extra cost and a specific design of passive devices. We propose an original solution to allow permanent and wide-range operations, with no need of any supplementary third coil to power supply the intelligent switch. This solution can be easily integrated in the same substrate within the power switch without special needs for insulation, bringing fairly good results in flyback converter applications based on the use of intelligent switches. In addition, the powering technique is used to clamp the turn-off overvoltage. The global converters operation takes advantage of the implementation of this new technique.

Integrated low power and high bandwidth optical isolator for monolithic power MOSFETs driver

An integrated solution for the galvanic isolation between power transistors and their control unit is presented in this paper. This solution is based on a monolithic integration of a photodetector within a power MOSFET without any modification of its fabrication process. This photoreceiver can be associated with a monolithic driver to drive high side switches. Exhaustive characteristics for several integrated photodetectors are presented and discussed: quantum efficiency, step response, small signal analysis and sensitivity to the High Voltage MOSFETs Drain. The results of this analysis are photoreceivers with a Full Width at Half Maximum above 300MHz and a responsivity above 0.15A/W at a wavelength of 500nm. This leads to an integrated low power and high bandwidth optical isolation.

Design and characterization of an integrated CMOS gate driver for vertical power MOSFETs

Currently, the trends in energy management are performance enhancement and increase in system reliability for the reduction of energy consumption. In this context, the integration of the gate driver within power transistors is particularly appropriate. This integration offers multiple advantages, from electrical and EMI performance improvement to power module size reduction, and reliability and functionality increase. This article presents a power MOSFET gate driver system developed with an approach which consists in including all the circuits required to drive a power switch on a single CMOS chip. The CMOS driver chip functionalities will be presented in this paper, and its design will be explained. Finally, experimental results of the fabricated chip used in a buck converter topology will be shown and discussed.

Experimental Investigation of an Integrated Optical Interface for Power MOSFET Drivers

To solve the galvanic isolation challenges in drivers related to gate signal transfer to power transistors, an optical detector was monolithically integrated within a 600 V vertical power transistor without any modifications in the fabrication process. After fabricating an initial prototype, preliminary static and dynamic characterization results have been investigated. The fabricated devices showed responsivities of 0.046 A/W at 0 V bias and 0.15 A/W at 15 V reverse bias and a bandwidth of at least 800 kHz when triggered with a 525 nm wavelength LED at an optical power in the microwatt range.

A vertical power device conductive assembly at wafer level using direct bonding technology

The paper presents current technological achievements and associated characterizations of the mechanical, thermal and electrical properties of the assembly at wafer level of vertical power devices matrices. Based on direct bonding technology, metallic substrates are bonded to the Silicon active layer at wafer level to ensure back-side common electrode electrical interconnections while offering outstanding electrical and thermal behavior. In addition, the characteristics of the power device can be optimized independently from mechanical requirements on Silicon thicknesses. The technological integration is described and analyzed. The paper focuses afterwards on the electrical characterizations of these new components. The interest of this partial packaging technique is related to the ease of implementation of numerous power devices used for example in interleaved converter topologies where up to ten to fourteen inverter arms can be connected in parallel to significantly reduce the needed filtering elements.

3D hybrid integration and functional interconnection of a power transistor and its gate driver

3D packaging and hybrid heterogeneous integration are currently attracting considerable interest in the literature. In most publications, the power dies and their respective gate drivers are interconnected using flex or PCB layers. Apart from a few exceptions, packaging is mainly based on separate power and driver dies, focusing on improving the performance of individual chips. This paper presents a different approach in which the design of the power and gate driver chips takes the interconnection of the two dies into account. This method is used in order to simplify and optimize packaging and interconnections and to improve the overall performance. The basic idea is to flip chip the integrated gate driver directly onto the power die, resulting in the 3D heterogeneous assembly of a vertical power device and a CMOS integrated gate driver. In order to simplify the implementation of this solution, the gate driver supply, its storage capacitor and the control signal insulation unit are also integrated and interconnected in and on the two silicon dies.

Integrated Photoreceiver For An Isolated Control Signal Transfert In Favour Of Power Transistors

The galvanic insulation around power transistors is often a requirement: the reference point of the power transistor may be at a high voltage level (series connected transistors or high voltage full bridges or inverters) and the insulation between the gate driver (operating at this reference point) and the external control part is fastidious. The optical insulation is a good candidate for high insulation levels, but this solution is costly while relaying on discrete implementations. In this paper, it is demonstrated how we have monolithically integrated a photoreceiver within a 600 V intelligent power device: first, a model has been developed (concerning the static and dynamical behaviors). Second, the model has been validated by a comparison with finite elements simulations (it has been used to forecast possible interactions with the main power part). Third, a 600 V power MOSFET with an integrated photoreceiver has been designed and manufactured, without any modification of the power transistors process. Simulations and modeling have been used to study and to analyze the interactions between the power device and the photoreciever integrated within its active region. Our prototypes have been checked out in practice. Added to an intelligent switch, this solution simplifies the implementation of power devices while reducing costs.