Nidhameddine Belhadj

H.264/AVC high definition intra coding implementation on multiprocessor system on chip technology architecture

Exploiting the multiprocessor system on chip technology (MPSoC) is a promising way to improve the frame rate of latest video encoders. In this article, an MPSoC architecture for the intra prediction encoding chain of H.264/AVC high definition is proposed using SoCLib, an open platform for virtual prototyping of MPSoC architectures. Experimental results show a speedup of about 85% in processing time, compared with an execution based on a single central processing unit, with an acceptable final circuit area. The proposed parallelism does not affect the quality of the reconstructed video and bit rate. It takes into account the data loading latency constraint and the size of used memory requirement. The proposed architecture is validated on FPGA technology, using a technique that allows switching from a virtual platform to a hardware one.

MPSoC Architecture for Macro Blocks Line Partitioning of H.264/AVC Encoder

Using multiprocessor technology is an interesting solution for reducing the processing time of complex video encoders such as H.264/Advanced Video Coding AVC. This paper details different levels of parallelism presented in related works for H.264/AVC encoder. An efficient Macro Blocks Line level parallelism for the intra prediction encoding chain of H.264/AVC for High Definition HD video is proposed. It is implemented on MPSoC architecture using an open and free platform for virtual prototyping named SoCLib. Comparing to related works, the proposed partitioning meets strongly the size of required memory constraint and provides an interesting speed-up. The proposed architecture is based on three processors and ensures a reduced circuit area. Experimental results reveal a run time saving of about 59.8% in terms of processing speed, compared to a classical execution based on a single CPU, without affecting the quality of the reconstructed video. Using multiprocessor technology is an interesting solution for reducing the processing time of complex video encoders such as H.264/Advanced Video Coding AVC. This paper details different levels of parallelism presented in related works for H.264/AVC encoder. An efficient Macro Blocks Line level parallelism for the intra prediction encoding chain of H.264/AVC for High Definition HD video is proposed. It is implemented on MPSoC architecture using an open and free platform for virtual prototyping named SoCLib. Comparing to related works, the proposed partitioning meets strongly the size of required memory constraint and provides an interesting speed-up. The proposed architecture is based on three processors and ensures a reduced circuit area. Experimental results reveal a run time saving of about 59.8% in terms of processing speed, compared to a classical execution based on a single CPU, without affecting the quality of the reconstructed video.

Statistical analysis of intra prediction in HEVC video encoder

High Efficiency Video Coding (HEVC) standard represents the newest video coding standard generation for both ITU-T Video Coding Experts Group and the ISO/IEC Moving Picture Experts Group. The new standard reduces bitrates by 50% compared to the existing standards using Advanced Video Coding (AVC) for equal video quality. This paper provides an overview of the technical features and characteristics of the new HEVC standard. A detailed statistical analysis of intra prediction unit showed that the RDO process represent the most time consuming module. Concerning intra prediction mode selection, the frequently chosen modes were 0, 1, 26, and 10. Then, the optimal mode represents on average 87% to belong to the most probable mode list MPM.

Data level parallelism for H264/AVC baseline intra-prediction chain on MPSoC

Currently, higher resolutions and faster frame rates are more and more demanded in real time video application. Consequently, encoder complexity and performance are the main penalties for such requirements. The emerging Multiprocessor System on Chip (MPSoC) architecture is a promising way for following the evolving video encoding applications, which can overcome the limitation of real-time processing with a single processor. Thus parallel computing for H.264/AVC encoder on multiprocessor is becoming a major research point that can resolve real time constraints. We contribute to this challenge by proposing MPSoC architecture for the intra prediction module, which is an important part of the H.264/AVC video encoder, using data level parallelism (DLP) approach. In this paper, we present an efficient partitioning of data for parallel processing for intra prediction; this approach is tested and evaluated on an open platform for virtual prototyping (SoCLiB). Experimental results show a gain of 74% in encoding speed when using four processors, and enabling minimum memory size and surface of MPSoC. Furthermore, our results highlight the relationship between the number of processors and the encoding run time.

Real-time H264/AVC high definition video encoder on a multicore DSP TMS320C6678

In this paper, the newest Texas Instruments multicore DSP TMS320C6678 is used in order to perform a real-time H264/AVC high definition (HD) embedded video encoder. We exploit the high computing performance offered by this eight-core DSP in order to meet the real-time encoding compliant. To enhance the encoding speed, Frame Level Parallelism (FLP) approach is applied. A master core is reserved to handle data transfers to/from DSP. Multithreading algorithm combined with a ping-pong buffers technique are exploited in order to optimize the standard FLP approach and hide communication overhead. Experimental results show that our enhanced FLP implementation allows achieving real-time HD (1280×720) video encoding by reaching up to 26 f/s (frame/second) as encoding speed. Experiments show also that our parallel implementation, performed on seven C6678 DSP cores running each @ 1 GHz, allows accelerating the encoding run-time by a factor of 6,38 without inducing any quality degradation or bit-rate increase.

H.264/AVC intra prediction encoding chain implementation on MPSoC based on slice level parallelism

Multiprocessor System on Chip (MPSoC) is a promising way to reduce the processing time required by digital multimedia encoders such the most complex H.264/Advanced Video Coding. MPSoC contributes in this challenge by offering a high performance computing, little system on chip (SoC) surface, and low power consumption. In order to reduce the execution time of H.264/AVC intra only encoding chain, an efficient parallel processing on MPSoC architecture is proposed in this paper. The proposed parallel processing is based on a mixed partitioning which combines slice and macro blocks line level parallelism. The proposed architecture is designed through SoCLib platform. For performances evaluation, three MIPS32 processors are used to accelerate the encoding time. Experimental results for High Definition (HD) video sequences show that the proposed implementation allows a saving of 65.7% in processing time compared to a single CPU execution. Furthermore, the proposed solution is characterized by a relatively low memory size which positively affects the final circuit surface.

MPSoC architecture for Component Level Parallelism of H.264/AVC intra prediction encoding chain on SoCLib platform

Nowadays, higher resolutions and faster processing time are more and more demanded in the field of video applications. Thus, algorithmic complexity of the encoder and its performances are the main penalties for such requirements. Recent woks show the efficiency of using the Multiprocessor System on Chip (MPSoC) technology to overcome the shortcomings of real-time processing with a single processor. We contribute to this challenge by proposing a MPSoC architecture for the intra prediction encoding chain, which is an important part of the H.264/AVC video standard. This MPSoC architecture is based on Component Level Parallelism (CLP) approach. This approach is tested and evaluated on SoCLib platform for virtual prototyping of MPSoC architectures. Experimental results show a gain of 32% in encoding speed when using two processors (CPUs), and enabling minimum memory size and MPSoC surface.

MPSoC architecture for H.264/AVC intra prediction chain on SoCLiB platform and FPGA technology

Multiprocessor System on Chip (MPSoC) technology can present an interesting solution to reduce the computational time of complex applications. Execute the H.264/AVC encoder on MPSoC architecture, is becoming an interesting point of research that can mitigate its algorithmic complexity and to resolve the real time constraints. In this paper, we present an efficient MPSoC architecture for the intra prediction process which is an important module of the H.264/AVC video encoder, using Data Level Parallelism (DLP) partitioning. This architecture is tested on an open platform for MPSoC architectures virtual designing (SoCLiB), and validated on FPGA technology. Experimental results show a gain of 74% in term of encoding speed when using four processors for coding a High Definition Video sequence (HDV) compared to uni-processor architecture.