Nouri Masmoudi

Fast prototyping H.264 Deblocking filter using ESL tools

This paper presents a design methodology for hardware/software (HW/SW) architecture design using ESL tools (Electronic System Level). From C++ descriptions, our design flow is able to generate hardware blocks running with a software part and all necessary codes to prototype the HW/SW system on Xilinx FPGAs. Therefore we use assistance of high level synthesis tools (Catapult C Synthesis), logic synthesis and Xilinx tools. As application, we developed an optimized Deblocking filter C code, designed to be used as a part of a complete H.264 video coding system [1]. Based on this code, we explored many configurations of Catapult Synthesis to analyze different area/time tradeoffs. Results show execution speedups of 95,5% compared to pure software execution etc.

TZSearch pattern search improvement for HEVC motion estimation modules

Motion estimation (ME) is a key operation for video compression. In fact, it contributes heavily to the compression efficiency by removing temporal redundancies. This process is the most critical part in a video encoder and can consume itself more than 50% of coding complexity or computational coding time. To reduce the computational time, many fast ME algorithms were proposed and implemented. The present paper proposes a fast ME algorithm that improves the basic Test Zone Search (TZS) ME algorithm which is considered to be one of the fastest ME algorithms and was implemented in HEVC reference software HM8.0. Experimental results show an improvement that can reach 8% up to 49% compared to the basic TZSearch.

Optimization and Implementation on Fpga of the DCT/IDCT Algorithm

In this paper, we present a comparison between two methods, the modified Loeffler algorithm (11 MUL and 29 ADD) and distributed arithmetic, to implement the DCT/IDCT algorithm for MPEG or H.26x video compression using VHDL description language. The implementation has been achieved on Altera Stratix EP1S10 FPGA which provides a dedicated DSP blocks required for common signal processing functions. A new solution based on this DSP blocks used to implement multipliers for the modified Loeffler algorithm in order to optimize speed and area

Hardware architecture for H.264/AVC deblocking filter algorithm

This paper presents novel hardware architecture for real-time implementation of adaptive deblocking filter algorithm used in H.264/AVC baseline profile video coding standard. This hardware is designed to be used as part of a complete H.264 video coding system for video conference applications. We use a novel edge filter ordering in a Macroblock to prevent the deblocking filter hardware from unnecessarily waiting for the pixels that will be filtered become available. This architecture presents minimum latency, maximum throughput, full utilization of hardware resources and combining both pipelining and parallel processing techniques. The proposed architecture is implemented in VHDL. The VHDL code is verified to work at 150 MHz in an ALTERA Stratix II FPGA.

DSP CAVLC implementation and optimization for H.264/AVC baseline encoder

Entropy coding is a fundamental stage in all video compression algorithms in terms of compression efficiency and error resilience. In this paper we propose and optimize a digital signal processor (DSP)-based implementation of the CAVLC tools for the H.264 Baseline encoder. As result, we have been able to generate the bit stream and supply bit rate result: the LETI encoder is able to achieve high compression performance when proposing interesting video quality.

HW/SW FPGA Architecture for a Flexible Motion Estimation

In this paper, we present a HW/SW implementation of the motion estimation on a FPGA circuit using the Nios II softcore processor. Furthermore, in multimedia processing, it is well-known that the sum of absolute differences (SAD) operation is the most time consuming operation when it is implemented in a software approach. Our implementation takes into account more than one algorithm of motion estimation processing and supports a parallel hardware implementation of the SAD operation. Our design is described in VHDL language, verified by simulation and implemented in a Stratix II EP2S60 FPGA circuit. The performances of our design have been tested using the H.263 video encoder.

Fast Intra Mode Decision Algorithm for H264/AVC HD Baseline Profile Encoder

The high performance of H.264/AVC video encoder is accompanied with a wide computation complexity especially for high definition (HD) video sequences. One of the major H.264/AVC features to be optimized is the mode decision for both inter and intra prediction. Thus, based on high correlation observed between selected inter prediction mode and intra mode decision, a fast intra mode decision algorithm based on the best inter prediction mode for H264 high definition (HD) baseline profile encoder is proposed. The evaluation of the proposed approach was based on the rate distortion and PSNR variation, execution time and percentage of skipping intra4x4 and intra16x16. The proposed scheme is performed on 720p (1280x720) and 1080p (1920x1088) HD video sequences. Experimental results show that the proposed algorithm can save up to 60% of intra prediction computation time, 16% of skipping intra16x16 and up to 83% for intra4x4 without inducing PSNR degradation and bit-rate increase. General Terms Video compression techniques and signal processing

An efficient pipeline execution of H.264/AVC intra 4×4 frame design

In this paper, we present an implementation of an optimized H.264 intra 4×4 algorithm in order to reduce the time of the intra 4×4 process. However the source of waste time in conventional architecture of intra 4×4 is the serialization of intra prediction and reconstruction of sixteen 4×4 blocks in one macroblock and the intra prediction of the current 4×4 block cannot be performed before the reconstruction of the previous 4×4 block. Therefore, for a high speed implementation we replaced the conventional one by a pipelined architecture while maintaining consistency with the standard. So we have studied ten alternative scanning orders based on rearranging order of intra 4×4 and we choose the best one which reduce dependencies between consecutively executed blocks without performance degradation. This order is implemented by a pipelined architecture using VHDL language. The VHDL code is verified to work at 100 MHz in an ALTERA Stratix II EP2S60F1020C3 FPGA. As a result, the processing time is reduced by 31.25% compared to the conventional implementation. So, it can be a good solution for real-time video application. The H.264 intra 4×4 hardware and software are demonstrated to work together on ALTERA NIOS-II development board with Stratix II EP2S60F1020C3 FPGA.

FPGA implementation of a HW/SW platform for multimedia embedded systems

This paper presents a HW/SW platform for embedded video system. It has been designed around an embedded RISC processor and FPGA technologies and provides video input and output interfaces. The configurable platform has been used to implement a real time video processing and vision systems. The Altera’s Nios II development board was chosen to realise this real time video platform which uses μClinux as embedded Linux Operating System. Experimental results using H.263 video encoder show that this platform provides enough resources and speed to implement even complex multimedia embedded systems in real time.

Hardware platform design for real-time video applications

In this paper, we present the installation of a hardware platform for video acquisition and restitution in real-time using a mixed software/hardware environment. The hardware platform is based on the Altera STRATIX development board. Besides, it is completed with a camera interface for acquisition and a VGA interface for restitution. The core of the system incorporates an IP module (intellectual property) of Altera Nios processor in the Quartus II development tool of Altera. During this study, we have used video sequences, which are acquired, processed and visualized while respecting temporal constraints.