Nijad Anabtawi

A simplified single-inductor dual-output DC-DC buck converter architecture with a fully digital Σ-Δ based controller

In this paper, a fully digital single-inductor dualoutput (SIDO) DC-DC Buck converter architecture is presented. The proposed converter features a simplified control loop that eliminates duplication of the controller sub blocks and allows for use of a single Pulse Width Modulator (PWM), compensator, and comparator to regulate the two outputs, therefore reducing overall system complexity. A 3rd order ΣΔ modulator was adopted for the implementation of the PWM generator resulting in spurious tone free operation. The ΣΔ modulator is implemented digitally with a minimum response delay time topology and reduced hardware complexity achieved through error masking and dithering. In addition, digitization of error signals in the control loop is achieved using non-feedback firstorder ΣΔ frequency Discriminators (SDFD) that are combined in an arrangement robust to process, voltage and temperature (PVT) variations. The design was implemented in 14nm technology and validated with simulations. Output voltage ripple is ~20mV and conversion efficiency 91%.

A fully implantable, NFC enabled, continuous interstitial glucose monitor

This work presents an integrated system-on-chip (SoC) that forms the core of a long-term, fully implantable, battery assisted, passive continuous glucose monitor. It integrates an amperometric glucose sensor interface, a near field communication (NFC) wireless front-end and a fully digital switched mode power management unit for supply regulation and on board battery charging. It uses 13.56 MHz (ISM) band to harvest energy and backscatter data to an NFC reader. System was implemented in 14nm CMOS technology and validated with post layout simulations.

An enhanced light-load efficiency step down regulator with fine step frequency scaling

This paper presents a switching DC-DC Buck converter with enhanced light-load efficiency for use in noise-sensitive applications. Low noise, spur free operation is achieved by using a sigma-delta-modulator (ΣΔ) based controller, while light load efficiency is realized through the introduction of fine step frequency scaling (FSFS) which continuously adjusts the switching frequency of the converter with load conditions. Regulation efficiency is further improved by adoption of mode hopping (continuous conduction mode (CCM)/ discontinuous conduction mode (DCM)) and utilization of a fully digital implementation. Furthermore, the presented converter maintains low output voltage ripple across its entire load range by reconfiguring the ΣΔ modulators quantization step and introducing dither to the loop filter. The proposed modulator was implemented in 14nm bulk CMOS process and validated with post layout simulations. It attains a peak efficiency of 95% at heavy load conditions and 79% at light loads with a maximum voltage ripple of 15mV at light loads.

An all-digital fast tracking switching converter with a programmable order loop controller for envelope tracking RF power amplifiers

This paper presents a step down, switched mode power converter for use in multi-standard envelope tracking radio frequency power amplifiers (RFPA). The converter is based on a programmable order sigma delta modulator that can be configured to operate with either 1st, 2nd, 3rd or 4th order loop filters, eliminating the need for a bulky passive output filter. Output ripple, sideband noise and spectral emission requirements of different wireless standards can be met by configuring the modulators filter order and converters sampling frequency. The proposed converter is entirely digital and is implemented in 14nm bulk CMOS process for post layout verification. For an input voltage of 3.3V, the converters output can be regulated to any voltage level from 0.5V to 2.5V, at a nominal switching frequency of 150MHz. It achieves a maximum efficiency of 94% at 1.5 W output power.

A single switcher combined series parallel hybrid envelope tracking amplifier for wideband RF power amplifier applications

In this paper, an improved architecture for RF power amplifier envelope tracking supply modulator is presented. It consists of a single switched mode supply regulator and one linear regulator. The switched mode supply regulator has two outputs, one of which is used in conjunction with the linear regulator to provide a wideband, high efficiency power supply to the RF amplifier, whereas the second output provides a band limited high efficiency supply to the linear regulator. The design offers improved power efficiency, reduced system complexity and area savings since the dual output switched mode regulator requires one inductor and a simple control loop. The design was implemented in 14nm CMOS process and validated with simulations. The supply modulator achieves a peak efficiency of 74% with a 6 dB PAPR 20MHz LTE signal at 29dBm output power.

An auditory nerve stimulation chip with integrated AFE, sound processing, and power management for fully implantable cochlear implants

This paper presents a system on chip for a fully implantable cochlear implant. It includes acoustic sensor frontend, 4-channel digital sound processing and auditory nerve stimulation circuitry. It also features a digital, switched mode, single inductor dual output power supply that generates two regulated voltages; 0.4 V used to supply on-chip digital blocks and 0.9 V to supply analog blocks and charge the battery when an external RF source is detected. All passives are integrated on-chip including the inductor. The system was implemented in 14nm CMOS and validated with post layout simulations.

An SET-free, fully-digital point-of-load regulator for next-generation spacecraft power systems

This paper presents a digitally controlled point-of-load regulator for next-generation power systems. It is intended for spacecraft with limited energy harvesting capability and on board battery storage such as micro- and nano-satellites as well as multi-tier power distribution networks of conventional satellite and spacecraft subsystems. The novel control loop was designed to minimize radiation induced single-event effects (SEE) and resulting transients. The design was implemented in 14nm bulk complimentary metal-oxide semiconductor (CMOS) process and validated with post layout simulations. It attains a peak efficiency of 95% at heavy load conditions and 79% at light loads with a maximum voltage ripple of 25mV at light loads. The most susceptible elements of the proposed regulator have a relatively high energy threshold (~ 15pJ corresponding to 40 MeV.cm2/mg) indicating a small probability of occurrence in harsh environments and no catastrophic failure.

Understanding video transmission decisions in cloud based computer vision services

This paper presents a study about the effect of the quality of the input video source on the computer vision system robustness and how to make use of the findings to create a framework generating a set of recommendation or rules for researchers and developers in the field to use. The study is of high importance especially for cloud based computer vision platforms where the transmission of raw uncompressed video is not possible, as such it is desired to have a sweet spot where the usage of bandwidth is at optimal level while maintaining high recognition rate. Experimental results showed that creating such rules is possible and beneficial to integrate in an end to end cloud based computer vision service.

An auto focus framework for computer vision systems

Capturing a clean video from a source camera is crucial for accurate results of a computer vision system. In particular, blurry images can considerably affect the detection, tracking and pattern matching algorithms. This paper presents a framework to apply quality control by monitoring captured video with the ability to detect whether the camera is out of focus or not, thus identifying blurry defective images and providing a feedback channel to the camera to adjust the focal length. The framework relies on the use of a no reference objective quality metric for the loopback channel to adjust the camera focus. The experimental results show how the framework enables reduction of unnecessary computations and thus enabling a more power efficient cameras.

Efficient shaped quantizer dithering implementation for sigma delta modulators

A well-known limitation of sigma delta modulators is the generation of limit cycle oscillations for DC and slow varying inputs. These limit cycles give rise to undesired tones at the output of the modulator which result in the deterioration of the signal to noise ratio (SNR). However, the use of high dither signal amplitude results in raising the in-band noise floor level. Based on the analysis presented in this paper, it is shown that the required dithering amplitude can be minimal depending on the oversampling ratio (OSR). Moreover, a new dither injection technique for sigma delta modulators is presented based on the analysis findings. The proposed circuit effectively eliminates the undesired tonal components of the modulator though the randomization of the comparators threshold levels. Simulation results using a first order single bit ΣΔ modulator show the suppression of the tonal components while deteriorating the SQNR by less than 1 dB.