Niko Joram

Design of a multi-band FMCW radar module

This paper presents a multi-band frequency-modulated continuous wave (FMCW) radar module. The module can perform ranging in a wide frequency range, including the 2.4GHz and 5.8GHz ISM bands. It incorporates an application specific integrated circuit (ASIC) for processing the analogue signals and a field programmable gate array (FPGA) as digital signal processing backend, providing a reconfigurable test platform. Using multiple stations, positioning measurements are performed which demonstrate the benefits of the multi-band system in different scenarios.

Integrated Adjustable Phase Shifters

When examining a monthly bank account statement, it is not only the number below the bottom line that matters. Whether that number has a minus or plus in front of it is crucial. For many technical problems, the sign matters as well. In circuits, we can change the sign by means of phase shifters. Moreover, by using phase shifters, intermediate states between the signs (including complex values) can be set in circuits. Hence, phase shifters play an important role in electrical engineering. Unfortunately, this article does not give direct insights to change the sign of your bank statement. However, it aims to give a comprehensive overview of tunable phase shifters for radio frequency (RF) applications including cookbooklike design guidelines and performance comparisons. The focus of this article is put on phase shifters fully integrated in a chip.

Fractional-N PLL optimization for highly linear wideband chirp generation for FMCW radars

This work addresses the optimization of Fractional-N Phase Locked Loops (Frac-N PLLs) used to produce frequency chirps for Frequency Modulated Continuous Wave (FMCW) radar applications. In a Frac-N PLL, we have two main clock domains which are the reference and the divided clock domains. Clock domain crossings have to be considered during chirp generation to produce highly linear chirps. Moreover, with wideband chirps, integer divide ratio increments during chirp generation may cause transient frequency glitches which also affect the chirp linearity if not taken care of. In this work we propose techniques to address these issues in Frac-N PLLs. The proposed techniques lead to highly linear wideband chirp generation and thus improve the distance calculation accuracy by a factor of 2 and the distance calculation precision by a factor of 1.5.

Fully integrated active CMOS vector modulator for 802.11a compliant diversity transceivers

In this paper, a CMOS vector modulator designed for smart antenna arrays at 5.5 GHz is presented. A quadrature all pass filter and sign select switches yield two orthogonal signal paths. Two variable gain amplifiers with strongly reduced phase shift of only ±6 ° are used to weight these paths. It has a phase control range of 360 ° and a gain range of −20 dB to 2.8 dB. The input-referred IP3 is −7 dBm at maximum gain. The current drawn from a 1.5 V supply amounts 12 mA. Using a 180 nm technology, the chip core area amounts 1.2×0.8 mm².

Fully integrated wideband sub-10 GHz radio frequency front end with active matching

This article presents an integrated radio frequency (RF) front end for the use in frequency bands up to 10GHz. It consists of an actively matched low noise amplifier (LNA) and a single multi-tanh Gilbert cell mixer. Its applications include frequency-modulated continuous wave (FMCW) radar front ends or single down conversion communication systems. The circuit is completely inductor-less. Using a negative resistance bandwidth enhancement technique, a 1dB bandwidth of 11.2 GHz is reached. The input reflection coefficient is below -7 dB up to a frequency of 7GHz within a printed circuit board (PCB) test bed. The single-sideband (SSB) noise figure amounts to 7dB and the small-signal gain is 26dB. The complete circuit is implemented using an IBM 180 nm SiGe BiCMOS process, occupies an active area of only 0.078 mm2 and consumes 57mW of DC power.

Integrated multi-band fractional-N PLL for FMCW radar systems at 2.4 and 5.8GHz

This article presents a fractional-N phase-locked loop (PLL) for the use in frequency-modulated continuous wave (FMCW) radar systems. The presented design supports division ratios from 59 to 4092 with a maximum input frequency of 7GHz, covering the 2.39GHz to 3.28GHz and 4.79GHz to 6.55GHz bands using a dual-band voltage-controlled oscillator (VCO) with a frequency resolution of 0.6Hz. This corresponds to a large relative bandwidth of more than 31%. Reference spur levels are lower than -65 dBc while phase noise is at -103 dBc/Hz at 1MHz offset frequency. A key feature for radar applications is the automatic chirp waveform generation. The complete circuit including VCO consumes less than 122mW and is implemented using an IBM 180 nm SiGe BiCMOS process.

Techniques for maximizing input handling and improving linearity of gain interpolating VGAs

This work presents gain interpolating variable gain amplifier (VGA) design aspects. A technique is introduced to improve the VGA input handling capability from a few hundred millivolts to rail-to-rail without affecting any other performance parameters and with low complexity. An additional technique is proven by hand analysis and simulations to reduce the 3rd order intermodulation products (IM3) of the VGA by 4dB. The VGA is designed in an IBM 0.13μm BiCMOS 7LM technology. It has a 56.5dB gain control range and draws 1.76mA from a 3V supply.

A SiGe wideband VCO and divider MMIC with low gain variation for multi-band systems at 2.4 and 5.8 GHz

A wideband LC voltage controlled oscillator (VCO) is presented in this work. Measurements show a wide relative tuning range of 37.6% from 4.57 GHz to 6.69 GHz with a tuning voltage from 0 to 3 V. Using an integrated divide-by-2 circuit, both the 2.4 GHz and 5.8 GHz ISM bands can be covered. A key feature is the low gain variation, which stays below 12.5 % up to 6GHz and below 33.3% for the whole tuning range. At 5.725 GHz, the phase noise at 1MHz offset was measured to -105dBc/Hz. The VCO core consumes 4mA of current from a 3V supply voltage. It is implemented using an IBM 180nm SiGe BiCMOS process and the core area amounts to 0.5mm×0.4 mm.

5.8 GHz demonstration system for evaluation of FMCW ranging

This work describes a demonstration platform for frequency-modulated continuous wave (FMCW) based ranging systems operating in the 5.8 GHz ISM band. The goal is to gain insight into system behavior and determine critical system parts prior to integration on chip. The versatility and configurability of the presented system allows testing different synchronization and ranging principles. A synchronization scheme is proposed which is robust against imperfections of the system. Distance measurements using this scheme are carried out in an indoor and outdoor scenario.

Crystal oscillator frequency offset compensation for accurate FMCW radar ranging

Accurate ranging and positioning systems encounter several practical limitations. Crystal oscillator (XO) tolerance is a major challenge that impairs the accuracy of these systems. Two-way ranging with frequency modulated continues wave (FMCW) radars in particular are more influenced by XO tolerance as compared to primary FMCW radars. So this work focuses on the measurement and compensation of the relative frequency offsets between the different XOs in FMCW radar systems in order to improve their ranging accuracy. With a two-way ranging synchronization protocol, a ±1 part per million (ppm) relative XO frequency offset may translate to ranging errors in the range of ±1.2 m. In this work, a three-way ranging synchronization protocol is proposed to compensate for the relative XO offset. The approach was tested in a practical ranging setup. Compared to the conventional two-way ranging synchronization protocol, the precision was enhanced by a factor of around 2.