Nikolaos D. Zervas

Evaluation of design alternatives for the 2-D-discrete wavelet transform

In this paper, the three main hardware architectures for the 2-D discrete wavelet transform (2-D-DWT) are reviewed. Also, optimization techniques applicable to all three architectures are described. The main contribution of this work is the quantitative comparison among these design alternatives for the 2-D-DWT. The comparison is performed in terms of memory requirements, throughput, and energy dissipation, and is based on a theoretical analysis of the alternative architectures and schedules. Memory requirements, throughput, and energy are expressed by analytical equations with parameters from both the 2-D-DWT algorithm and the implementation platform. The parameterized equations enable the early but efficient exploration of the various tradeoffs related to the selection to the one or the other architecture.

Data-Reuse and Parallel Embedded Architectures for Low-Power, Real-Time Multimedia Applications

Exploitation of data re-use in combination with the use of custom memory hierarchy that exploits the temporal locality of data accesses may introduce significant power savings, especially for data-intensive applications. The effect of the data-reuse decisions on the power dissipation but also on area and performance of multimedia applications realized on multiple embedded cores is explored. The interaction between the data-reuse decisions and the selection of a certain data-memory architecture model is also studied. As demonstrator a widely-used video processing algorithmic kernel, namely the full search motion estimation kernel, is used. Experimental results prove that improvements in both power and performance can be acquired, when the right combination of data memory architecture model and data-reuse transformation is selected.

A local wavelet transform implementation versus an optimal row-column algorithm for the 2D multilevel decomposition

A new method for the implementation of the binary-tree decomposition of the convolution-based wavelet transform, called the local wavelet transform (LWT) has been recently proposed in the literature. While it produces exactly the same results as the classical row-column implementation of the transform, it has many implementation benefits. This fact is shown experimentally for the first time for a general-purpose processor-based architecture, by comparing our C implementation of the LWT with an optimal C implementation of the lifting-scheme row-column algorithm. The comparisons are made for the forward multilevel binary-tree decomposition using the 9/7 filter pair, in the typical Intel Pentium processor family.

A Code Transformation-Based Methodology for Improving I-Cache Performance of DSP Applications

This paper focuses on I-cache behaviour enhancement through the application of high-level code transformations. Specifically, a flow for the iterative application of the I-Cache performance optimizing transformations is proposed. The procedure of applying transformation is driven by a set of analytical equations, which receive parameters related to code and I-cache structure and predict the number of I-cache misses. Experimental results from a real-life demonstration application shows that order of magnitude reductions of the number of I-cache misses can be achieved by the application of the proposed methodology.

Memory hierarchy exploration for low power architectures in embedded multimedia applications

Multimedia applications are characterized by an increased number of data transfer and storage operations due to real time requirements. Appropriate transformations can be applied at the algorithmic level to improve crucial implementation characteristics. The effect of the data-reuse transformations on power consumption, area and performance of multimedia applications realized on embedded cores is examined. As demonstrators, widely applicable video processing algorithmic kernels, namely the row-column decomposition DCT and its fast implementation found in MPEG-X, are used. Experimental results prove that significant improvements in power consumption can be achieved without performance degradation by the application of data-reuse transformations in combination with the use of a custom memory hierarchy.

Analytical exploration of power efficient data-reuse transformations on multimedia applications

Power savings that can be achieved by data-reuse decisions targeting at a custom memory hierarchy for multimedia applications executing on embedded cores are examined in this paper. Exploiting the temporal locality of memory accesses in data-intensive applications a set of data-reuse transformations on a typical motion estimation algorithm is determined. The aim is to reduce data related power consumption by moving background memory accesses to smaller foreground memories, which are less power costly. The impact of these transformations on power, performance and area is evaluated both for application specific circuits and general purpose processors. The number of data and instruction memory accesses is analytically calculated, enabling a fast exploration of the design space by varying algorithmic parameters.

A methodology for the behavioral-level event-driven power management of digital receivers

Power management is a low-power technique applicable in almost all design levels. Event-driven power management has been applied at the system-level. The same concept can be applied for receiver design at the behavioral-level. Power management involves a trade-off according to which, on the one hand, power is decreased by shutting down parts of the circuit, but on the other hand, power is increased by the insertion of the required logic for the generation of the shutdown signals. In this paper, receiver context characteristics are exploited in order to develop a methodology for the behavioral-level exploration of this trade-off. The efficiency of the proposed methodology is proven by its application on a real-life digital DECT receiver.

Data and instruction memory exploration of embedded systems for multimedia applications

A methodology for power optimization of the data memory hierarchy and instruction memory, is introduced. The effect of the methodology on a set of widely used multimedia application kernels, namely full search, hierarchical search, and parallel hierarchical one dimension search, is demonstrated. Three different target architecture models are used. The issues of the data memory power reduction and instruction memory are tackled separately. We find the power optimal data memory hierarchy applying the appropriate data-use transformation, while the instruction power optimization is done using suitable cache memory. Using data-reuse transformations, performance optimization techniques, and instruction-level transformations, we perform exhaustive exploration of all the possible alternatives to reach power efficient solutions. The experimental results prove the efficiency of the methodology in terms of power for all the multimedia kernels.

Power exploration of multimedia applications realized on embedded cores

Low power realization of video applications on embedded cores is described. Code transformations are applied to reduce the data memory power consumption. The transformed code indicates a power efficient data memory architecture while transformations move the main part of memory accesses from larger memories (possibly off-chip) to smaller ones (on-chip). The effect of transformations on performance, which is usually the overriding issue in such systems, is evaluated. It is shown that performance is closely related to program memory power consumption that is in some case orders of magnitude larger than data memory power consumption. The aim of the proposed research is the development of a methodology for the application of data storage and transfer optimizing transformations that achieve a close to optimal balance between power and performance in realizations of multimedia applications on embedded cores.

Power exploration of parallel embedded architectures implementing data-reuse transformations

Efficient use of data-reuse transformations combined with a custom memory hierarchy that exploits the temporal locality of data related memory accesses can have a significant impact on system power consumption, especially in data dominated applications e.g. multimedia processing. In this paper the effect of data-reuse decisions on power consumption, area and performance of multimedia applications implemented on uni- and dual-processor embedded cores is explored. By this work it is clarified that conclusions for the transformations effect on multi-processor architectures can be extracted by the corresponding effect on the uniprocessor architecture. In this way the exploration space can be significantly reduced. A motion estimation algorithm, namely the two-dimensional logarithmic search, and a discrete cosine transform (DCT) algorithm are used as demonstrator applications.