Adonios Thanailakis

A model for predicting forest fire spreading using cellular automata

Abstract The model presented, for the first time, in this paper can predict the spreading of fire in both homogeneous and inhomogeneous forests and can easily incorporate weather conditions and land topography. An algorithm has been constructed based on the proposed model and was used for the determination of fire fronts in a number of hypothetical forests, which were found to be in good agreement with the experience on fire spreading in real forests.

Collision-free path planning for a diamond-shaped robot using two-dimensional cellular automata

This paper presents a new parallel algorithm for collision-free path planning of a diamond-shaped robot among arbitrarily shaped obstacles, which are represented as a discrete image, and its implementation in VLSI. The proposed algorithm is based on a retraction of free space onto the Voronoi diagram, which is constructed through the time evolution of cellular automata, after an initial phase during which the boundaries of obstacles are identified and coded with respect to their orientation. The proposed algorithm is both space and time efficient, since it does not require the modeling of objects or distance and intersection calculations. Additionally, the proposed twodimensional multistate cellular automaton architecture achieves high frequency of operation and it is particularly suited for VLSI implementation due to its inherent parallelism, structural locality, regularity, and modularity.

Data-Reuse and Parallel Embedded Architectures for Low-Power, Real-Time Multimedia Applications

Exploitation of data re-use in combination with the use of custom memory hierarchy that exploits the temporal locality of data accesses may introduce significant power savings, especially for data-intensive applications. The effect of the data-reuse decisions on the power dissipation but also on area and performance of multimedia applications realized on multiple embedded cores is explored. The interaction between the data-reuse decisions and the selection of a certain data-memory architecture model is also studied. As demonstrator a widely-used video processing algorithmic kernel, namely the full search motion estimation kernel, is used. Experimental results prove that improvements in both power and performance can be acquired, when the right combination of data memory architecture model and data-reuse transformation is selected.

A cellular automaton for the determination of the mean velocity of moving objects and its VLSI implementation

Abstract A new algorithm for the determination of the mean velocity of a moving object, using the properties of Cellular Automata, is presented in this paper. The mean velocity is calculated along the centra axis perpendicular to the lens of the vision system. The motion of the object is restricted to translation (angular velocity is zero) and to one moving object in the scene. Experimental results for the determination of the mean velocity and its computational error are also presented. The algorithm presented in this paper does not require the calculation or the extraction of image features, such as area and shape, line segments, characteristic points, corners, etc. The design and VLSI implementation of a Cellular Automaton architecture is also presented for the efficient realisation of the algorithm.

The circuit design of multiple-valued logic voltage-mode adders

Novel quaternary half adder, full adder, and a carry-lookahead adder are introduced. The proposed circuits are static and operate in voltage-mode. Moreover, there is no current flow in steady states, and thus no static power dissipation. Although the comparison in transistor count shows that the proposed quaternary circuits are larger than two respective binary ones, benefits in parallel addition arise from the use of multiple-valued logic. Firstly, the ripple-carry additions are faster because the number of carries are half compared to binary ones and the delay from the input carry through the output carry is relatively small. Secondly, the carry-lookahead scheme exhibits less complexity, which leads to overall reduction in transistor count for addition with a large number of bits.

Simulation of the image reversal submicron process in integrated circuit fabrication

An algorithm for the simulation of the image reversal process based on Cellular Automata is presented for the first time. The development resist profiles produced by this algorithm are of the same geometry and shape as those obtained by experiments. Furthermore, the dependence of the slope of a resist-line-edge on the bake time has also been successfully reproduced using this algorithm.

A new hardware module for automated visual inspection based on a cellular automaton architecture

This paper presents the design and VLSI implementation of a new automated visual inspection system based on a cellular automaton architecture, suitable for circular object inspection. Cellular Automata (CA) transform the area of the object of interest into a number of evolution steps in the CA space. The proposed technique does not require the extraction of image features, such as boundary length and total area, which are computationally expensive in other methods. The die size dimensions of the chip, for a 16×16 pixel image, are 3.73 mm×3.09 mm=11.52 mm2 and its maximum frequency of operation is 25 MHz. Experimental results using computer-generated images, as well as real images obtained and processed through a commercial vision system, showing the suitability of the proposed hardware module for detecting circular objects, are also presented. Targeted applications include inspection tasks (accept/reject operations) of circular objects, such as tablets in the pharmaceutical industry, and detection of uncoated areas, foreign objects and level of bake in the confectionery and food industry.

A review of amorphous silicon alloys: Fabrication, properties and applications

A review of amorphous silicon alloys (other than a-Si: H) is presented. The main focus is on experimental results. Methods of fabricating amorphous alloys are classified and their basic operational principles outlined. The electrical and optical properties of amorphous silicon based alloys are then described, and a summary of existing and potential applications given. Conspicuous gaps in the fabrication, understanding and application of these materials are pointed out. A comprehensive (though not exhaustive) bibliography is presented, with references to all amorphous silicon alloys studied up to the summer of 1986.

Systematic methodology for designing low power direct digital frequency synthesisers

The overall operation of a direct digital frequency synthesiser (DDFS) is based on a look-up table method, which performs functional mapping from phase to sine amplitude. The spectral purity of the conventional DDFS is determined by the resolution of the values stored in the sine table ROM. However, large ROM storage means higher power consumption, increased silicon area, lower reliability, lower speed and increased costs. A novel systematic design methodology for implementing a DDFS architecture with reduced memory size is introduced. Describing the proposed architecture using the hardware description language VHDL, it is possible to generate a plethora of alternative realisations in terms of the number of input and output bits, the memory size, the number of gates, the memory segmentation parameters and the spectral purity. In other words, the designer can perform extensive architecture exploration to reach an optimal solution. The experimental results prove that the new DDFS architecture can be realised with a smaller hardware complexity and total power consumption and improved performance compared to many existing approaches.

DAGGER: a novel generic methodology for FPGA bitstream generation and its software tool implementation

A novel bitstream generation algorithm and its software implementation are introduced. Although this tool was developed for the configuration of AMDREL FPGA reconfigurable platform, it could be used to program any other compatible device. This tool is the only one known academic implementation for FPGA configuration with such features. Among them are the run-time-, partial- and dynamic-reconfiguration, the memory management, the bitstream compression and encryption, the read-back technique, the bitstream reallocation, the used low-power techniques as well as the graphical user interface.