Niu Jin

Diffusion barrier cladding in Si/SiGe resonant interband tunneling diodes and their patterned growth on PMOS source/drain regions

Si/SiGe resonant interband tunnel diodes (RITDs) employing /spl delta/-doping spikes that demonstrate negative differential resistance (NDR) at room temperature are presented. Efforts have focused on improving the tunnel diode peak-to-valley current ratio (PVCR) figure-of-merit, as well as addressing issues of manufacturability and CMOS integration. Thin SiGe layers sandwiching the B /spl delta/-doping spike used to suppress B out-diffusion are discussed. A room-temperature PVCR of 3.6 was measured with a peak current density of 0.3 kA/cm/sup 2/. Results clearly show that by introducing SiGe layers to clad the B /spl delta/-doping layer, B diffusion is suppressed during post-growth annealing, which raises the thermal budget. A higher RTA temperature appears to be more effective in reducing defects and results in a lower valley current and higher PVCR. RITDs grown by selective area molecular beam epitaxy (MBE) have been realized inside of low-temperature oxide openings, with performance comparable with RITDs grown on bulk substrates.

Tri-state logic using vertically integrated Si-SiGe resonant interband tunneling diodes with double NDR

A vertically integrated npnp Si-based resonant interband tunneling diode (RITD) pair is realized with low-temperature molecular beam epitaxy by stacking two RITDs with a connecting backward diode between them. The current-voltage characteristics of the vertically integrated RITD pair demonstrates two sequential negative differential resistance regions in the forward-biasing condition. Tri-state logic is demonstrated by using the vertically integrated RITDs as the drive and an off-chip resistor as the load.

151 kA/cm2 peak current densities in Si/SiGe resonant interband tunneling diodes for high-power mixed-signal applications

Room-temperature I–V characteristics of epitaxially grown Si/SiGe resonant interband tunneling diodes (RITDs) with extremely high peak current densities are presented. By optimizing the physical design, doping concentrations, and post-growth anneal temperatures, RITDs having peak current densities over 150 kA/cm2, peak-to-valley current ratios (PVCRs) greater than 2, and an estimated speed index of 34 mV/ps have been obtained. The interplay among the conditions to achieve maximum current density and highest PVCR is discussed. This result demonstrates the high potential of this type of Si-based tunnel diode for high-power mixed-signal applications.

Three-terminal Si-based negative differential resistance circuit element with adjustable peak-to-valley current ratios using a monolithic vertical integration

Si-based resonant bipolar transistors are demonstrated by the monolithic vertical integration of Si-based resonant interband tunnel diodes atop the emitter of Si/SiGe heterojunction bipolar transistors (HBTs) on a silicon substrate. In the common emitter configuration, IC versus VCE shows negative differential resistance characteristics. The resulting characteristics are adjustable peak-to-valley current ratios, including infinite and negative values, and tailorable peak current densities by the control of the HBT base current under room temperature operation. With the integrated RITD-HBT combination, latching properties which are the key operating principle for high-speed mixed-signal, memory, and logic circuitry, are experimentally demonstrated.

The Effect of Spacer Thicknesses on Si-Based Resonant Interband Tunneling Diode Performance and Their Application to Low-Power Tunneling Diode SRAM Circuits

Si-based resonant interband tunneling diodes (RITD) with spacer thicknesses varying from 1 to 16 nm were grown and fabricated. The effect of spacer thickness on the peak-to-valley current ratio (PVCR), peak current density Jp, and voltage swing was studied. By increasing the tunneling spacer thickness up to 16 nm, RITDs with a J p of as low as 20 mA/cm2 with an associated PVCR of 1.6 were obtained, which are suitable for low-power tunnel diode SRAM applications. With the previously reported highest RITD Jp of 218 kA/cm2, a Jp spanning nearly seven orders of magnitude can be obtained by engineering the tunneling spacer thickness and doping densities, thus demonstrating tremendous flexibility to optimize Jp for different circuit applications (logic, memory, and mixed-signal). Using a low-current-density RITD developed in this paper, a bread-boarded one-transistor tunneling-based SRAM (TSRAM) memory cell with low standby power consumption was demonstrated. This is the first report of a Si-based TSRAM memory circuit using Si-based RITDs. The result demonstrates the potential of Si-based tunnel diodes for low-power memory applications

Si/SiGe resonant interband tunnel diode with f/sub r0/ 20.2 GHz and peak current density 218 kA/cm/sup 2/ for K-band mixed-signal applications

This letter presents the room-temperature high-frequency operation of Si/SiGe-based resonant interband tunnel diodes that were fabricated by low-temperature molecular beam epitaxy. The resulting devices show a resistive cutoff frequency f/sub r0/ of 20.2 GHz with a peak current density of 218 kA/cm/sup 2/, a speed index of 35.9 mV/ps, and a peak-to-valley current ratio of 1.47. A specific contact resistivity of 5.3/spl times/10/sup -7/ /spl Omega//spl middot/cm/sup 2/ extracted from RF measurements was achieved by Ni silicidation through a P /spl delta/-doped quantum well by rapid thermal sintering at 430/spl deg/C for 30 s. The resulting devices are very good candidates for RF high-power mixed-signal applications. The device structures presented here are compatible with a standard complementary metal-oxide-semiconductor or heterojunction bipolar transistor process.

Annealing of defect density and excess currents in Si-based tunnel diodes grown by low-temperature molecular-beam epitaxy

Deep-level transient spectroscopy (DLTS) measurements were performed in order to investigate the effects of post-growth heat treatment on deep level defects in Si layers grown by low-temperature molecular-beam epitaxy (LT-MBE) at 320 °C. In the LT-MBE as-grown samples, two dominant divacancy-related complex defects, of which the possible origins are suggested as P–V (E center)+V–V (0/−) and V–V (−2/−) and others, were observed in P-doped n layers. When the as-grown samples were annealed at 700, 800, and 900 °C for 60 s by rapid thermal annealing, the total density of defects were decreased without generating other defects and most defects were annihilated at 900 °C. This study also compared the DLTS trends with performance of Si-based resonant interband tunnel diodes (RITDs) in terms of peak current density, valley current density, and peak-to-valley current ratio, which are closely related to the deep-level defects. The active regions of the RITDs were grown at the same substrate growth temperature and a...

Growth temperature and dopant species effects on deep levels in Si grown by low temperature molecular beam epitaxy

Deep-level transient spectroscopy measurements were performed in order to investigate the effects of substrate growth temperature and dopant species on deep levels in Si layers during low-temperature molecular beam epitaxial growth. The structures studied were n+-p junctions using B doping for the p layer and p+-n junctions using P doping for the n layer. While the density of hole traps H1 (0.38–0.41 eV) in the B-doped p layers showed a clear increase with decreasing growth temperature from 600 to 370 °C, the electron trap density was relatively constant. Interestingly, the minority carrier electron traps E1 (0.42–0.45 eV) and E2 (0.257 eV), found in the B-doped p layers, are similar to the majority carrier electron traps E11 (0.48 eV) and E22 (0.269 eV) observed in P-doped n layers grown at 600 °C. It is hypothesized that these dominating electron traps are associated with pure divacancy defects and are independent of the dopant species.

High sensitivity Si-based backward diodes for zero-biased square-law detection and the effect of post-growth annealing on performance

High-sensitivity Si-based backward diodes were realized that are monolithically integratable with transistor circuitry. Potential applications include large area focal plane arrays. The Si-based backward diodes exhibit a high zero-biased curvature coefficient, /spl gamma/, of 31 V/sup -1/ and a low zero biased junction capacitance, C/sub j/, of 9 fF//spl mu/m/sup 2/, all at room temperature. The predicted low frequency voltage sensitivity, /spl beta//sub V/, for a 50 /spl Omega/ source is 3100 V/W. The high sensitivity, low junction capacitance, and Si/SiGe heterojunction bipolar transistor compatibility of the Si-based backward diodes make them very attractive for zero-bias square-law detector applications.

Analysis of the Voltage Swing for Logic and Memory Applications in Si/SiGe Resonant Interband Tunnel Diodes Grown by Molecular Beam Epitaxy

A method is investigated to directly engineer the voltage swing in SiGe resonant interband tunnel diodes (RITDs). Voltage swing, defined here as the voltage difference between the peak voltage and the projected peak voltage, is independent of series resistance, and thus directly impacts the noise margin in hybrid tunnel diode memory and logic applications. The three components of the total RITD current are analyzed to describe the voltage swing. The dependence of voltage swing on delta-doping concentrations and post-growth annealing temperatures in SiGe RITDs grown by low-temperature molecular beam epitaxy (LT-MBE) is investigated and the experimental results are compared with a theoretical analysis. Techniques to increase the voltage swing are discussed