Nobutaka Taniguchi

Timing clock generation circuit using hierarchical DLL circuit

Integrated circuit device incorporating dll circuit

Semiconductor device having timing-stabilization circuit and method of testing such semiconductor device

Delay time adjusting method of delaying a phase of an output signal until a phase difference between an input signal and the output signal becomes an integral number of periods other than zero

Method for adjusting phase of controlling clock signal and semiconductor integrated circuit having delay locked loop circuit

Integrated circuit device provided with dll circuit

Semiconductor device using external power voltage for timing sensitive signals

Integrated circuit device with built-in dll circuit

Delay time adjusting circuit comprising frequency dividers having different frequency division rates

Multi-value nonvolatile semiconductor memory device equipped with reference cell and load balancing circuit