Nobuyoshi Matsuura

System in package with mounted capacitor for reduced parasitic inductance in voltage regulators

A system in package (SiP) on which an input capacitor is mounted has been developed for voltage regulators. The SiP offers the worlds lowest power dissipation of 3.8 W at 1 MHz. Its parasitic inductance is 44% lower than SiPs with the input capacitor mounted on the PCB, due to a small loop from the input capacitor to the MOSFETs, which reduces power dissipation by 25% at the same peak voltage. The high-side MOSFET die is flipped so that the drain electrode faces up, facilitating the connection of the MOSFET to the input capacitor. The lead frames and MOSFETs are connected with Cu leads, which reduce the spreading resistance of the MOSFET electrodes.

System in Package (SiP) With Reduced Parasitic Inductance for Future Voltage Regulator

A system in package (SiP) that integrates high-side and low-side MOSFETs and their driver IC has been developed for voltage regulators. Compared with the conventional discrete package, the SiP offers 25% lower power loss because it has low parasitic inductances. The peak drain voltage of the low-side MOSFET during turn- on of the high-side MOSFET is 45% lower than that of the discrete package, and this improves switching noise characteristics and lowers MOSFET conduction losses because it decreases the MOSFET breakdown voltage. A mixed-mode simulation was performed that indicated the common-source parasitic inductance should be reduced in order to attain low switching loss. To reduce this common-source parasitic inductance, the source pad of the high-side MOSFET is bonded directly to the driver IC with a wire.

Low loss and small SiP for DC-DC converters

This paper presents a SiP (system in package) that integrates high-side and low-side MOSFETs and a driver IC. The developed SiP has been realized the smallest mount area and lowest loss of DC-DC converter compared with the conventional devices that have ever been reported. Low-inductance packaging technology and optimization of the MOSFETs and driver IC by the MCM method (MCM: mixed simulation of circuit and MOS-power-devices), reduce the mount area by 60% smaller and reduce the loss by 25% compared with conventional discrete devices, when Vin=12 V, Vout=1.3 V, Iout=25 A, f=1 MHz.

Advanced Power SiP with Wireless Bonding for Voltage Regulators

An advanced power system in package (SiP) for voltage regulators is presented; it offers the worlds lowest power dissipation of 4.4 W at 1 MHz, with an output voltage of 1.3 V and an output current of 25 A. Its package resistance is 88% lower due to using Cu leads for the bonding, which reduces the spreading resistance of the MOSFET. The diode loss is 43% lower due to using a Schottky barrier diode incorporated into the low-side MOSFET. The thermal resistance is also 43% lower due to using a large topside Cu lead.

A System-in-Package (SiP) With Mounted Input Capacitors for Reduced Parasitic Inductances in a Voltage Regulator

This paper presents a system-in-package (SiP) that mounts an input capacitor for voltage regulators. The SiP has a low power loss of 3.8 W at a switching frequency of 1 MHz, input voltage of 12 V, and output current of 25 A. The parasitic inductance of this SiP is 56% that of the previously reported SiP, which had the input capacitor mounted on the printed circuit board, and this reduction is due to the short current loop from the input capacitor to the MOSFETs. As a result, the power loss can be reduced by 20% for the same spike voltage. The high-side MOSFET die is flipped so that the drain electrode faces up, facilitating the connection of the drain electrode of the high-side MOSFET and the source electrode of the low-side MOSFET to the mounted input capacitor. The authors also propose a way to estimate the parasitic inductance experimentally, not from a current measurement such as with a shunt resistor and a current probe, but from the ringing frequency when the high-side MOSFET is switched and the output capacitance C oss of the MOSFET being on the off state.

A Cu-Plate-Bonded System-in-Package (SiP) With Low Spreading Resistance of Topside Electrodes for Voltage Regulators

This paper presents a system-in-package (SiP) with Cu-plate bonding for voltage regulators. The SiP reduces the power loss by 23% and the thermal resistance by 44% compared to those of a SiP with wire bonding. Copper plates reduce the spreading resistance of the topside electrodes in the MOSFETs, leading to lower power loss. They also act as heat spreaders, leading to lower thermal resistance. The lower power loss and lower thermal resistance contribute toward decreasing a topside temperature that is 18.5°C less than that of a wire-bonded SiP. The Cu plate in the low-side MOSFET has a slit at the center that reduces solder strain between the die and lead frame by 12%. The Cu plates in the high-side and low-side MOSFETs have bumps projecting into the solder layer, resulting in a solder layer that is uniform and thick enough to relax the solder strain.

System in Package with Mounted Capacitor for Reduced Parasitic Inductance in Voltage Regulators

A system in package (SiP) on which an input capacitor is mounted has been developed for voltage regulators. The SiP offers the worlds lowest power dissipation of 3.8 W at 1 MHz. Its parasitic inductance is 44% lower than SiPs with the input capacitor mounted on the PCB, due to a small loop from the input capacitor to the MOSFETs, which reduces power dissipation by 25% at the same peak voltage. The high-side MOSFET die is flipped so that the drain electrode faces up, facilitating the connection of the MOSFET to the input capacitor.

Low reverse recovery charge 30-V power MOSFETs for DC-DC converters

Two low reverse recovery charge solutions for 30-V power MOSFETs are proposed. One solution is a device consisting of a MOSFET and a Schottky barrier diode (SBD) in a single chip featuring a double epi structure to enhance the breakdown voltage. The other solution is a device with an integrated SBD in every unit cell that can achieve a high threshold voltage via the P- layer with Schottky contact. Both proposed devices exhibited low reverse recovery currents in simulations. Moreover, the surge voltage of the first device which we fabricated reduced by 58%, which enables the use of a lower voltage device and a reduction of the device loss.