Yoshito Nakazawa
Renesas Electronics
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Publication
Featured researches published by Yoshito Nakazawa.
international symposium on power semiconductor devices and ic's | 2011
T. Tamaki; Yoshito Nakazawa; H. Kanai; Y. Abiko; Y. Ikegami; M. Ishikawa; E. Wakimoto; T. Yasuda; S. Eguchi
600V-class superjunction (SJ) MOSFETs fabricated by trench-filling process are investigated by analytical and numerical solutions with experimental results. The careful consideration on the effects of trench taper and p-column profile is given for accurate charge control. The breakdown voltage (Vb), specific on-resistance (RonAa), and gate-to-drain charge (Qgd) of 736 V, 16.4 mΩ-cm2, and 6 nC, respectively, have been achieved for the fabricated SJ-MOSFET.
international symposium on power semiconductor devices and ic s | 2016
Katsumi Eikyu; Atsushi Sakai; Hitoshi Matsuura; Yoshito Nakazawa; Yutaka Akiyama; Yasuo Yamaguchi; M. Inuishi
The very narrow mesa structures based on our 7th generation IGBT process are fabricated and it is found that the device with the narrowest mesa shows very poor short circuit (SC) withstand capability although it suppresses the conduction loss considerably. This poor SC capacity is caused by non-saturated output characteristics which are originated by collector bias induced barrier lowering in the middle of Si mesa. The current filamentation is observed in the 3D multi-cell short circuit simulation with self-heating and the SC capacity degradation due to the filamentation is enhanced in the narrower mesa structure.
Archive | 2012
Hitoshi Matsuura; Yoshito Nakazawa
Archive | 2015
Hitoshi Matsuura; Makoto Koshimizu; Yoshito Nakazawa
Archive | 2011
Hitoshi Matsuura; Yoshito Nakazawa
Archive | 2008
Atsushi Shinbori; Yoshito Nakazawa
Archive | 2006
Masaki Shiraishi; Takayuki Iwasaki; Nobuyoshi Matsuura; Yoshito Nakazawa; Tsuyoshi Kachi
Archive | 2013
Satoshi Eguchi; Yoshito Nakazawa; Tomohiro Tamaki
Archive | 2011
Tomohiro Tamaki; Yoshito Nakazawa
Archive | 2003
Tomoaki Uno; Yoshito Nakazawa