Norbert Wermes

Single photon counting X-ray imaging with Si and CdTe single chip pixel detectors and multichip pixel modules

Multichip modules (MCM) have been successfully built and operated. These use 4 single-photon counting MPEC 2.3 chips that are bump bonded to 1.3 cm /spl times/ 1.3 cm CdTe or Si semiconductor pixel sensors. Single-chip detectors were built as well. The MPEC 2.3 chip provides a pixel count rate up to 1 MHz with a large dynamic range of 18 bits, 2 counters and energy windowing with continuously adjustable thresholds. Each MPEC has 32 /spl times/ 32 pixels of 200 /spl mu/m /spl times/ 200 /spl mu/m pixel size. For a MCM the 4 chips are arranged in a 2 /spl times/ 2 array which leads to a 64 /spl times/ 64 sensor pixel geometry. The MCM construction is described, and the imaging performance of the different detectors is shown. A newly developed USB readout system has been used.

Counting and integrating readout for direct conversion X-ray imaging concept, realization and first prototype measurements

A novel signal processing concept for X-ray imaging with directly converting pixelated semiconductor sensors is presented. The novelty of this approach compared to existing concepts is the combination of charge integration and single photon counting in every single pixel. Simultaneous operation of both signal processing chains extends the dynamic range beyond the limits of the individual schemes and allows determination of the mean photon energy. Medical applications such as X-ray computed tomography can benefit from this additional spectral information through improved contrast and the ability to determine the hardening of the tube spectrum due to attenuation by the scanned object. A prototype chip in 0.35-micrometer technology was successfully tested. The pixel electronics are designed using a low-noise differential current mode logic and provide configurable feedback modes, leakage current compensation and various test circuits. This paper will discuss measurement results of the prototype structures and give details on the circuit design

A counting pixel readout chip for imaging applications

Abstract A pixel readout chip for imaging applications has been designed and tested. It consists of an array of 12 × 63 pixels with an active pixel cell area of 50 μ m × 350 μ m. Every pixel contains a low-noise charge sensitive amplifier, a CMOS comparator including individually adjustable thresholds, and a 15 bit counter realized using a linear feedback shift register. During data accumulation, every pixel independently counts the number of signal hits above threshold. After accumulation all counters in a column are sequentially read out, all columns in parallel. Thresholds can be set globally with the possibility of an individual threshold adjust in every cell. The chip can be operated with threshold settings in every cell well below equivalent noise charges (ENC) of 1000 electrons. The dead time of a pixel after being hit is ∼500 ns. The chip is alive for data accumulation in > 99.9% of the total data acquisition time. For photon counting in biomedical or material science applications, a suitable sensor with high Z material can be bump bonded to the counting chip.

Pixel detectors for particle physics and imaging applications

Semiconductor pixel detectors offer features for the detection of radiation which are interesting for particle physics detectors as well as for imaging e.g., in biomedical applications (radiography, autoradiography, protein crystallography) or in X-ray astronomy. At the present time hybrid pixel detectors are technologically mastered to a large extent and large-scale particle detectors are being built. Although the physical requirements are often quite different, imaging applications are emerging and interesting prototype results are available. Monolithic detectors, however, offer interesting features for both fields in future applications. The state of development of hybrid and monolithic pixel detectors, excluding CCDs, and their different suitability for particle detection and imaging, is reviewed.

A photon counting pixel chip with energy windowing

A method allowing single photon counting with additional energy information without increasing the radiation dose is presented. On a pixel chip an energy window has been realised by introducing a second discriminator with a separate counter in every pixel. Both discriminators have an independent threshold voltage and can be adjusted individually. Measurements on the noise behavior, threshold variation and threshold settings are presented.

A fast readout using switched current techniques for a DEPFET-pixel vertex detector at TESLA

A fully depleted silicon detector with a first amplifying transistor integrated in every pixel (DEPFET) is a promising proposal for the pixel-based vertex detector at TESLA. The DEPFET offers good spatial resolution, an excellent signalto-noise ratio and low power consumption in a row-wise operation mode. A readout concept for a DEPFET pixel array matching the requirements at TESLA is described. In order to meet the operation specifications at TESLA (50 MHz row rate), a readout architecture based on current mode techniques (Switched Current) is presented. It contains stand alone zero suppression offering a triggerless operation. The core of the readout chip, a fast operating current memory cell, is discussed in detail. The results of a first prototype chip, CURO I (CUrrent ReadOut), show that the requirements for TESLA are achievable. r 2003 Elsevier B.V. All rights reserved.

DEPFET Active Pixel Detectors for a Future Linear

The DEPFET collaboration develops highly granular, ultra-transparent active pixel detectors for high-performance vertex reconstruction at future collider experiments. The characterization of detector prototypes has proven that the key principle, the integration of a first amplification stage in a detector-grade sensor material, can provide a comfortable signal to noise ratio of over 40 for a sensor thickness of 50-75 μm. ASICs have been designed and produced to operate a DEPFET pixel detector with the required read-out speed. A complete detector concept is being developed, including solutions for mechanical support, cooling, and services. In this paper, the status of the DEPFET R & D project is reviewed in the light of the requirements of the vertex detector at a future linear e+e- collider.

e^{+}e^{-}

Field effect transistors embedded into a depleted silicon bulk (DEPFETs) can be used as the first amplifying element for the detection of small signal charges deposited in the bulk by ionizing particles, X-ray photons or visible light. Very good noise performance at room temperature due to the low capacitance of the collecting electrode has been demonstrated. Regular two-dimensional arrangements of DEPFETs can be read out by turning on individual rows and reading currents or voltages in the columns. Such arrangements allow the fast, low-power readout of larger arrays with the possibility of random access to selected pixels. In this paper, different readout concepts are discussed as they are required for arrays with incomplete or complete clear and for readout at the source or the drain. Examples of VLSI chips for the steering of the gate and clear rows and for reading out the columns are presented.

Collider

Three-dimensional (3-D) silicon detectors are characterized by cylindrical electrodes perpendicular to the surface and penetrate into the bulk material in contrast to standard Si detectors with planar electrodes on the top and bottom. This geometry renders them particularly interesting to be used in environments where standard silicon detectors have limitations, such as, for example, the radiation environment expected in an upgrade to the Large Hadron Collider at CERN. For the first time, several 3-D sensors were assembled as hybrid pixel detectors using the ATLAS-pixel front-end chip and readout electronics. Devices with different electrode configurations have been characterized in a 100 GeV pion beam at the CERN SPS. Here, we report results on unirradiated devices with three 3-D electrodes per 50times400 mum2 pixel area. Full charge collection is obtained already with comparatively low bias voltages around 10 V. Spatial resolution with binary readout is obtained as expected from the cell dimensions. Efficiencies of 95.9%plusmn0.1% for tracks incident parallel to the electrodes and of 99.9%plusmn0.1% for tracks incident at 15deg are measured. The homogeneity and charge sharing of the efficiency over the pixel area are measured.

Readout concepts for DEPFET pixel arrays

A new pixel front-end integrated circuit is being developed in a 130 nm technology for use in the foreseen b-layer upgrade of the ATLAS pixel detector. Development of this chip is considered as an intermediate step towards super-LHC upgrade, and also allows having a smaller radius insertable pixel layer. The higher luminosity for which this chip is tuned implies a complete redefinition of the digital architecture logic with respect to the current ATLAS pixel front-end. The new digital architecture logic is not based on a transfer of all pixel hits to the periphery of the chip, but on local pixel logic, local pixel data storage, and a new mechanism to drain triggered hits from the double-column. An overview of the new chip will be given with particular emphasis on the new digital logic architecture and possible variations. The new interface needed to configure and operate the chip will also be described.