Tomasz Hemperek

Digital architecture and interface of the new ATLAS Pixel Front-End IC for upgraded LHC luminosity

A new pixel front-end integrated circuit is being developed in a 130 nm technology for use in the foreseen b-layer upgrade of the ATLAS pixel detector. Development of this chip is considered as an intermediate step towards super-LHC upgrade, and also allows having a smaller radius insertable pixel layer. The higher luminosity for which this chip is tuned implies a complete redefinition of the digital architecture logic with respect to the current ATLAS pixel front-end. The new digital architecture logic is not based on a transfer of all pixel hits to the periphery of the chip, but on local pixel logic, local pixel data storage, and a new mechanism to drain triggered hits from the double-column. An overview of the new chip will be given with particular emphasis on the new digital logic architecture and possible variations. The new interface needed to configure and operate the chip will also be described.

A Monolithic Active Pixel Sensor for ionizing radiation using a 180 nm HV-SOI process

Abstract An improved SOI-MAPS (Silicon On Insulator Monolithic Active Pixel Sensor) for ionizing radiation based on thick-film High Voltage SOI technology (HV-SOI) has been developed. Similar to existing Fully Depleted SOI-based (FD-SOI) MAPS, a buried silicon oxide inter-dielectric (BOX) layer is used to separate the CMOS electronics from the handle wafer which is used as a depleted charge collection layer. FD-SOI MAPS suffers from radiation damage such as transistor threshold voltage shifts due to charge traps in the oxide layers and charge states created at the silicon oxide boundaries (back gate effect). The X-FAB 180-nm HV-SOI technology offers an additional isolation by deep non-depleted implant between the BOX layer and the active circuitry which mitigates this problem. Therefore we see in this technology a high potential to implement radiation-tolerant MAPS with fast charge collection property. The design and measurement results from a first prototype are presented including charge collection in neutron irradiated samples.

The FE-I4 pixel readout system-on-chip resubmission for the insertable B-Layer project

The FE-I4 is a new pixel readout integrated circuit designed to meet the requirements of ATLAS experiment upgrades. The first samples of the FE-I4 engineering run (called FE-I4A) delivered promising results in terms of the requested performances. The FE-I4 team envisaged a number of modifications and fine-tuning before the actual exploitation, planned within the Insertable B-Layer (IBL) of ATLAS. As the IBL schedule was pushed significantly forward, a quick and efficient plan had to be devised for the FE-I4 redesign. This article will present the main objectives of the resubmission, together with the major changes that were a driving factor for this redesign. In addition, the top-level verification and test efforts of the FE-I4 will also be addressed.

Digital architecture of the new ATLAS pixel chip FE-I4

With the high hit rate foreseen for the innermost layers at an upgraded LHC, the current ATLAS Front-End pixel chip FE-I3 [1] would start being inefficient. The main source of inefficiency comes from the copying mechanism of the pixel hits from the pixel array to the end of column buffers. A new ATLAS pixel chip FE-I4 is being developed in a 130 nm technology for use both in the framework of the Insertable B-Layer (IBL) project and for the outer layers of Super-LHC. FE-I4 is made of 80×336 pixels and features a reduced pixel size of 50×250 μm2. In the current design, a new digital architecture is introduced in which hit memories are distributed across the entire pixel array and the pixels organized in regions. In this paper, the digital architecture of FE-I4 is presented as well as the complete data flow.

The RD53 Collaboration's SystemVerilog-UVM Simulation Framework and its General Applicability to Design of Advanced Pixel Readout Chips

The foreseen Phase 2 pixel upgrades at the LHC have very challenging requirements for the design of hybrid pixel readout chips. A versatile pixel simulation platform is as an essential development tool for the design, verification and optimization of both the system architecture and the pixel chip building blocks (Intellectual Properties, IPs). This work is focused on the implemented simulation and verification environment named VEPIX53, built using the SystemVerilog language and the Universal Verification Methodology (UVM) class library in the framework of the RD53 Collaboration. The environment supports pixel chips at different levels of description: its reusable components feature the generation of different classes of parameterized input hits to the pixel matrix, monitoring of pixel chip inputs and outputs, conformity checks between predicted and actual outputs and collection of statistics on system performance. The environment has been tested performing a study of shared architectures of the trigger latency buffering section of pixel chips. A fully shared architecture and a distributed one have been described at behavioral level and simulated; the resulting memory occupancy statistics and hit loss rates have subsequently been compared.

Prototype Active Silicon Sensor in 150 nm HR-CMOS technology for ATLAS Inner Detector Upgrade

The LHC Phase-II upgrade will lead to a significant increase in luminosity, which in turn will bring new challenges for the operation of inner tracking detectors. A possible solution is to use active silicon sensors, taking advantage of commercial CMOS technologies. Currently ATLAS R&D programme is qualifying a few commercial technologies in terms of suitability for this task. In this paper a prototype designed in one of them (LFoundry 150 nm process) will be discussed. The chip architecture will be described, including different pixel types incorporated into the design, followed by simulation and measurement results.

The Data Handling Processor for the Belle II Pixel Vertex Detector: efficiency optimization

A major upgrade of the current Japanese B-Factory (KEK-B) is planned for 2015. Together with this new machine (SuperKEK-B) also a new detector, Belle-II, will be operated to fully exploit the planned luminosity of 8 × 1035 s−1cm−2 (40 times larger than previously). One of the major changes in the new experiment will be the introduction of a new sub-detector, close to the interaction point, to allow a precise reconstruction of the decay vertices of the B meson systems. This pixel detector, based on the DEPFET technology, will consist of 20 ladder modules arranged in two cylindrical layers around the beam pipe. Each of the modules will be read-out independently by a combination of analog and digital ASICs placed at both ends of each sensor. The digital chip, the Data Handling Processor (DHP), is designed to control the readout chain and to pre-process and to compress the data. The chip structure and the latest results about its performance optimization will be presented.

Charge collection properties of a depleted monolithic active pixel sensor using a HV-SOI process

New pixel detector concepts, based on commercial high voltage and/or high resistivity CMOS processes, are being investigated as a possible candidate to the inner and outer layers of the ATLAS Inner Tracker in the HL-LHC upgrade. A depleted monolithic active pixel sensor on thick film SOI technology is being extensively investigated for that purpose. This particular technology provides a double well structure, which shields the thin gate oxide transistors from the Buried Oxide (BOX). In addition, the distance between transistors and BOX is one order of magnitude bigger than conventional SOI technologies, making the technology promising against its main limitations, as radiation hardness or back gate effects. Its radiation hardness to Total Ionizing Dose (TID) and the absence of back gate effect up to 700 Mrad has been measured and published [1]. The process allows the use of high voltages (up to 300V) which are used to partially deplete the substrate. The process allows fabrication in higher resistivity, therefore a fully depleted substrate could be achieved after thinning. This article shows the results on charge collection properties of the silicon bulk below the BOX by different techniques, in a laboratory with radioactive sources and by edge Transient Current Technique, for unirradiated and irradiated samples.

Neutron irradiation test of depleted CMOS pixel detector prototypes

Charge collection properties of depleted CMOS pixel detector prototypes produced on p-type substrate of 2 kΩ cm initial resistivity (by LFoundry 150 nm process) were studied using Edge-TCT method before and after neutron irradiation. The test structures were produced for investigation of CMOS technology in tracking detectors for experiments at HL-LHC upgrade. Measurements were made with passive detector structures in which current pulses induced on charge collecting electrodes could be directly observed. Thickness of depleted layer was estimated and studied as function of neutron irradiation fluence. An increase of depletion thickness was observed after first two irradiation steps to 1 1013 n/cm2 and 5 1013 n/cm2 and attributed to initial acceptor removal. At higher fluences the depletion thickness at given voltage decreases with increasing fluence because of radiation induced defects contributing to the effective space charge concentration. The behaviour is consistent with that of high resistivity silicon used for standard particle detectors. The measured thickness of the depleted layer after irradiation with 1 1015 n/cm2 is more than 50 μm at 100 V bias. This is sufficient to guarantee satisfactory signal/noise performance on outer layers of pixel trackers in HL-LHC experiments.

Digital Architecture and Interface of the New ATLAS Pixel Front-End IC for Upgraded LHC Luminosity

A new pixel Front-End Integrated Circuit is being developed in a 130nm technology for use in the foreseen b-layer upgrade of the ATLAS Pixel Detector. Development of this chip is considered as an intermediate step towards super-LHC upgrade, and also allows having a smaller radius insertable pixel layer. The higher luminosity for which this chip is tuned implies a complete redefinition of the digital architecture logic with respect to the current ATLAS pixel Front-End. The new digital architecture logic is not based on a transfer of all pixel hits to the End-of-Column, but on local pixel logic, local pixel data storage, and a new mechanism to drain triggered hits from the Double-Column. An overview of the new chip will be given with particular emphasis on the new digital logic architecture and possible variations. The new interface needed to configure and operate the chip will also be described.