Norio Yokozawa

A 500-MHz 8-bit D/A converter

An ultrafast monolithic 8-bit DAC is designed and fabricated. To realize this DAC, a new high-speed conversion technique, referred to as the data multiplexing method, and a variation of the segmented DAC (J.A. Shoeff, 1979) for low glitch are developed. The DAC is fabricated with shallow-groove-isolated 3-/spl mu/m VLSI technology with peak f/SUB T/s of 4.5 GHz. An experimental 8-bit DAC features a conversion rate of over 500 MHz, a full-scale settling time to 1% of 2 ns, rise/fall times of 0.6 ns, and a glitch energy of 20 ps-V without input latches or a deglitcher.

Principle of High-Speed Digital Subtraction Echography and the Potential for Clinical Applications

To improve time and spatial resolution of echography, we have developed a High-speed Digital Subtraction Echography. The principle is serial image subtraction of successive frames of high-speed B-mode echograms. This system elucidated: 1) initial myocardial contraction originating from the pacing point of an experimental ventricular premature contraction (VPC) in dogs. Substantially the same initial contraction appeared from the VPC focus in a human patient. 2) Local elasticity of arterial wall was assessed as the systolic fine radial extension. 3) Utilizing echoic particles in blood, the streamlines were also visualized.