Kenji Maio

A 10-bit 20-MHz two-step parallel A/D converter with internal S/H

A 10-bit 20-MHz A/D converter for high-quality video systems such as high-definition television, video tape recorders for business use, and digital video cameras is described. This LSI circuit uses a standard two-step parallel architecture, includes automatic gain adjustment and digital two-bit error correction, and has a sample-and-hold circuit on the chip. It is fabricated by a 4.5-GHz f/sub T/. 3- mu m-rule standard bipolar technology. Its die size is 25 mm/sup 2/, and its power consumption is 900 mW, which is about half of the lowest values reported to date. The converter can digitize video signals of up to 8.5 MHz at a conversion frequency of 20 MHz. The error in differential gain is 0.5 percent, and the error in differential phase is 0.5 degrees . >

A 150-mW, 8-bit video-frequency A/D converter

The authors describe an 8-bit, extremely low-power, flash A/D converter LSI for video-frequency image signal processing. This converter uses a shallow-groove-isolated bipolar VLSI technology. It consumes only 150 mW, which is half the amount of the lowest power consumption so far reported. This low level of power consumption is achieved by the use of a comparator circuit, which is newly designed. This converter can digitize video signals of up to 10 MHz at a conversion rate of 30 MHz. A differential gain (DG) error of 1% and a differential phase (DP) error of less than 0.5/spl deg/ were observed.

A 500-MHz 8-bit D/A converter

An ultrafast monolithic 8-bit DAC is designed and fabricated. To realize this DAC, a new high-speed conversion technique, referred to as the data multiplexing method, and a variation of the segmented DAC (J.A. Shoeff, 1979) for low glitch are developed. The DAC is fabricated with shallow-groove-isolated 3-/spl mu/m VLSI technology with peak f/SUB T/s of 4.5 GHz. An experimental 8-bit DAC features a conversion rate of over 500 MHz, a full-scale settling time to 1% of 2 ns, rise/fall times of 0.6 ns, and a glitch energy of 20 ps-V without input latches or a deglitcher.

Novel automatic tuning method of RC filters using a digital-DLL technique

A novel automatic tuning method for RC filters is proposed for CMOS low-IF transceivers. The method is based on a digital-DLL-like technique and tunes the time constant of filters automatically. The tuning range and the tuning accuracy are analyzed theoretically. To verify the method, a sixth-order 2-MHz IF filter for Bluetooth and a tuning circuit were fabricated in 0.18-/spl mu/m CMOS. The tuning circuit occupying 0.066 mm/sup 2/ includes only a reference first-order filter, a comparator, and a simple digital circuit. The measurement result of the filter and the tuning circuit shows that the maximum /spl plusmn/28% time-constant variation can be tuned within /spl plusmn/5% accuracy, which is consistent with theoretical results.

Automatic tuning of RC filters and fast automatic gain control for CMOS low-IF transceiver

Automatic tuning of RC filters and fast automatic gain control (AGC) of cascaded programmable amplifiers were proposed and verified by a 0.18 /spl mu/m CMOS prototype IC. The tuning circuit includes a dummy 1st-order filter, a comparator and a simple digital circuit and tunes /spl plusmn/28 % time-constant variation of filters within /spl plusmn/4.4 % accuracy. The AGC circuit adopts a novel feedforward technique with a digital timing control, which enables one-shot gain control and thus a fast settling.

0.18-/spl mu/m CMOS Bluetooth analog receiver with -88-dBm sensitivity

A CMOS Bluetooth analog low-IF receiver that includes a low-noise amplifier, image-rejection mixer, IF bandpass active filter, and programmable gain amplifier (PGA) was fabricated in a 0.18-/spl mu/m bulk CMOS process. In order to achieve good sensitivity and tolerance against blocking signals, operational amplifiers were used in the active filter and PGA, the filter and PGA were interleaved to minimize noise, and an on-chip automatic tuner adjusts the filter frequency. Other features included a feedforward automatic gain control with rapid convergence. When connected to the digital demodulator of a BiCMOS Bluetooth transceiver, -88-dBm sensitivity was measured at 65-mW power dissipation. All blocking signal specifications were also satisfied.

A 10b 3MSample/s CMOS cyclic ADC

This low-power, small-area, 10 b 3 MSample/s (0.33 /spl mu/s) CMOS on-chip ADC uses an improved recursive subranging approach. A multi-path cyclic-conversion architecture, an implementation of a recursive subranging architecture, is proposed to further reduce the power by reducing the required circuit speed. As a result, this ADC achieves compatibility between the low-power and small-area requirements. For on-chip system application, a module that includes bus interface circuitry and buffer amplifiers for the reference-voltage generators is implemented in addition to the 10 b 3 MSample/s ADC.

Gain calibration and feedforward automatic gain control for CMOS radio-frequency ICs

Two circuits for improving the performance of a Bluetooth CMOS RFIC are described. A RF amplifier gain calibration circuit uses a dummy amplifier to calibrate voltage gain and output voltage swing. The dummy amplifiers and a target RF amplifier share the bias circuit, thereby allowing accurate RF gain control against temperature, bias and process variations. A 0.18 /spl mu/m CMOS calibration circuit achieved gain control within +/-0.5 dB. The second circuit, an interleafed multi-stage filter and IF amplifier for use in a low-IF receiver, has an AGC circuit with a novel feedforward control that allows rapid convergence of the amplifier gain. When applied to a Bluetooth signal, convergence was achieved within 5 /spl mu/s even in the worst case blocking signal condition.

A 500MHz 8b DAC

A DAC with a 500MHz conversion rate, 2ns settling time, 0.6ns rise/fall times and 200ps/V glitch energy will be reported. The DAC has been fabricated in shallow groove VLSI technology.

An untrimmed DAC with 14b resolution

A monolithic 14b D/A converter which is self-compensated without trimming analog components will be described. The device has been fabricated with analog compatible I²L technology, affording a linearity error within<tex>± 1/2</tex>LSB or± 0.003%.