Norman Chen

Implementation of CDSEM contour extraction on OPC verification

CDSEM metrology is a powerful tool to obtain silicon data. However, as our technology nodes advance shrink to 14nm and below, the CD measurement data from CDSEM can hardly provide sufficient information for OPC verification (OPCV) and the related silicon verification. On the other hand, the abundant information from CDSEM images has not been fully utilized to assist our data analysis. In this context, contour extraction emerges as the best method to obtain extensive information from CDSEM images, especially for 2D structures. This paper demonstrates that contour extraction bridges the gap between the needs of 2D characterization and the limited capability of CDSEM measurement. The extracted contour enables automatic identification of litho-hotspots using OPCV tools, especially for non-CD related hotspots. Statistical silicon data extraction and analysis on complex geometries is viable with extracted contours. The silicon data can then be feedback to the evolution of non-CD OPCV checks, where simple CD measurement is inadequate. Effective CD can also be calculated from the obtained 2D information, with which Bossung curves can be built and provide complementary information.

Strategies for single patterning of contacts for 32nm and 28nm technology

As 193 nm immersion lithography is extended indefinitely to sustain technology roadmaps, there is increasing pressure to contain escalating lithography costs by identifying patterning solutions that can minimize the use of multiple-pass processes. Contact patterning for the 32/28 nm technology nodes has been greatly facilitated by just-in-time introduction of new process enablers that allow the support of flexible foundry-oriented ground rules alongside high-performance technology, without inhibiting migration to a single-pass patterning process. The incorporation of device based performance metrics along with rigorous patterning and structural variability studies were critical in the evaluation of material innovation for improved resolution and CD shrink. Additionally novel design changes for single patterning along new capability in data preparation were both assessed to leverage minimal impact of implementation of a single patterning contact process into the existing 32nm and 28nm technology programs [1].

Contact patterning strategies for 32nm and 28nm technology

As 193 nm immersion lithography is extended indefinitely to sustain technology roadmaps, there is increasing pressure to contain escalating lithography costs by identifying patterning solutions that can minimize the use of multiple-pass processes. Contact patterning for the 32/28 nm technology nodes has been greatly facilitated by just-in-time introduction of new process enablers that allow the simultaneous support of flexible foundry-oriented ground rules alongside highperformance technology, while also migrating to a single-pass patterning process. The incorporation of device based performance metrics along with rigorous patterning and structural variability studies were critical in the evaluation of material innovation for improved resolution and CD shrink along with novel data preparation flows utilizing aggressive strategies for SRAF insertion and retargeting.

Using heuristic optimization to set SRAF rules

A heuristic optimization approach has been developed to optimize SRAF (sub resolution assist feature) placement rules for advanced technology nodes by using a genetic algorithm. This approach has demonstrated the capability to optimize a rule-based SRAF (RBSRAF) solution for both 1D and 2D designs to improve PVBand and avoid SRAF printing. Compared with the MBSRAF based POR (process of record) solution, the optimized RBSRAF can produce a comparable PVBand distribution for a full chip test case containing both random SRAM and logic designs with a significant 65% SRAF generation time reduction and 55% total OPC time reduction.

Effects of focus difference of nested and isolated features for scanner proximity matching

Assuming that all exposure tools on which a certain production reticle is being used are from same type and configuration it can be expected that the performance of the reticle should be independent from the exposing machines. When planning or performing arrangements for process transfer between different production sites or capacity expansion within one site performing a proximity matching between different exposure tools is a common activity. One of the objectives of a robust optical proximity correction (OPC) model is to simulate the process variation. Normally, the wafer critical dimension (CD) calibration of an OPC model is applied for one specific scanner first. In order to enhance the tolerance of the OPC model so called fingerprints of different scanners should be matched as closely as possible. Some examples of features for fingerprint test patterns are “critical dimension through pitch” (CDTP), “inverse CDTP”, “tipto-tip” and “linearity patterns”, and CD difference of disposition structures. All of them should also be matched as tightly as possible in order to reduce the process variation and to strengthen the tolerance of an OPC model. However, the focus difference between nested and isolated features which is directly influenced by different exposure tools and reticle layers will have an effect on the proximity matching of some patterns such as inverse CDTP and uniformly distributed disposition structures. In this manuscript the effects of focus differences between nested and isolated features for scanner proximity matching will be demonstrated. Moreover, the results for several scanners and different mask layers using advanced binary mask blank material will also be investigated. Even if some parts of the proximity features are closely enough to each other different parity proximity patterns will be affected by the focus difference between dense and isolated features. Because the focus difference between isolated and dense features is dependent on the illumination conditions, different mask layers applied for a proximity correction will lead to different results. The effects of source variations causing isolated and dense feature focus differences between scanners for 28 nm poly, 1X metal and contact layers will be illustrated.

Escaping death: single-patterning contact printing for 32/28-nm logic technology nodes

As 193-nm immersion lithography is extended indefinitely to sustain technology roadmaps, there is increasing pressure to contain escalating lithography costs by identifying patterning solutions that can minimize the use of multiple-pass processes. Contact patterning for the 32/28-nm technology nodes has been greatly facilitated by the just-in-time introduction of new process enablers that allow the support of flexible foundry-oriented ground rules alongside high-performance technology, without inhibiting migration to a single-pass patterning process. The incorporation of device-based performance metrics, along with rigorous patterning and structural variability studies, was critical in the evaluation of material innovation for improved resolution and CD shrink. Additionally, novel design changes for single patterning incorporating mask optimization efforts, along with new capability in data preparation, were assessed to allow for minimal impact of implementation of a single patterning contact process late in the 32-nm and 28-nm development cycles. In summary, this paper provides a comprehensive study of what it takes to turn a contact-level double-patterning process into a single-patterning process consisting of design and data manipulation, as well as wafer manufacturing aspects, together with many results.

Suppressing rippling with minimized corner rounding through OPC fragmentation optimization

As technology shrinks, the requirements placed on the post-OPC solution become so exacting that even small residual optical effects are significant. Simultaneously minimizing rippling and corner rounding cannot be accom- plished in parallel in wafer patterning especially when complex asymmetric pixelated sources are used. While either effect can be moderated by accurate application of optical proximity correction, they are both charac- teristic of unfiltered diffraction due to asymmetric illumination or design geometry and will remain inherent. Corrections that over emphasize reduced corner-rounding necessarily sacrifice edge convergence, resulting in a standing wave or unacceptable rippling along an entire edge. OPC can be used to reduce the magnitude of this rippling, but fragment placing is extremely critical. In this paper, we discuss optimized OPC fragmentation that offers balanced consideration to suppressing rippling and minimizing corner rounding. Specifically, we correlate design shapes with simulated post-OPC contours to account for design geometry-dependent rippling signature given existing illumination conditions. In contrast to adaptive fragmentation that relies on multiple iterations of simulation of intensity extrema redistribution, our method predicts the optimum contour as allowed by process and fragments the mask accordingly. The maximum imaging curvature resolvable by process coupled with the rippling signature, gives rise to the exact locations of the inflection points of the wafer contour. From there we achieve the best correction results by segmenting edges at the inflection points.

Wafer weak point detection based on aerial images or WLCD

Aerial image measurement is a key technique for model based optical proximity correction (OPC) verification. Actual aerial images obtained by AIMS (aerial image measurement system) or WLCD (wafer level critical dimension) can detect printed wafer weak point structures in advance of wafer exposure and defect inspection. Normally, the potential wafer weak points are determined based on optical rule check (ORC) simulation in advance. However, the correlation to real wafer weak points is often not perfect due to the contribution of mask three dimension (M3D) effects, actual mask errors, and scanner lens effects. If the design weak points can accurately be detected in advance, it will reduce the wafer fab cost and improve cycle time. WLCD or AIMS tools are able to measure the aerial images CD and bossung curve through focus window. However, it is difficult to detect the wafer weak point in advance without defining selection criteria. In this study, wafer weak points sensitive to mask mean-to-nominal values are characterized for a process with very high MEEF (normally more than 4). Aerial image CD uses fixed threshold to detect the wafer weak points. By using WLCD through threshold and focus window, the efficiency of wafer weak point detection is also demonstrated. A novel method using contrast range evaluation is shown in the paper. Use of the slope of aerial images for more accurate detection of the wafer weak points using WLCD is also discussed. The contrast range can also be used to detect the wafer weak points in advance. Further, since the mean to nominal of the reticle contributes to the effective contrast range in a high MEEF area this work shows that control of the mask error is critical for high MEEF layers such as poly, active and metal layers. Wafer process based weak points that cannot be detected by wafer lithography CD or WLCD will be discussed.