Randy W. Mann

Bias-Induced Healing of

A novel bias-induced healing of address specific failing bits in VLSI SRAM functional arrays is demonstrated for the first time in advanced CMOS nodes. Aging effects due to bias temperature instability (BTI) resulting in device shifts are a well-known reliability problem in advanced CMOS technologies. We propose and demonstrate a method of exploiting the BTI mechanism and the addressing capability of SRAM to recover bits that fail during stress. Recovery of failures using this method is demonstrated in both 20- and 14-nm technology nodes in VLSI SRAM arrays. This method introduces the possibility of self-healing SRAM arrays and overcomes many of the limitations of the conventional industry voltage-guard-band approach.

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Aggressive technology and supply voltage scaling has led to increasing concern for reliability. Optimizing power and energy with sub-threshold (sub-VT) operation exponentially increases the occurrences of both static and dynamic failures. With smaller node capacitances with each technology and supply scaling node, radiation-induced Single Event Upset (SEU) has become a critical design metric for Ultra-Low-Power (ULP) applications. In this paper, we explore the impact of radiation-induced soft errors on sub-threshold SRAM implemented in a Body Sensory Node (BSN) as an ULP application. We also demonstrate an exponential reduction in the critical charge (Qcrit) of a storage node with supply in near- and sub-VT design, resulting in a significant design consideration for the low-power applications. The huge process variation in sub-VT results in 3X Qcrit variation. Finally, we compare the trend of technology scaling and supply voltage scaling on Qcrit.

Failures in Advanced SRAM Arrays

An essential goal of the static random access memory (SRAM) array termination design is to both terminate as well as maintain a homogeneous environment for the active edge cells in the array. Local layout effects (LLEs) in the array termination design can exert influence on the active array SRAM devices in close proximity to the termination region, which can lead to undesirable inhomogenuities in the array. The impact of LLEs, originating from the array termination design, on SRAM read performance and

Soft errors: Reliability challenges in energy-constrained ULP body sensor networks applications

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Array Termination Impacts in Advanced SRAM

fail count, are examined using a 14-nm FinFET technology. Large-scale SRAM read performance statistics are analyzed to identify elevated read currents and low-voltage fail counts associated with the array termination. The root cause and modulating factors are explored, and potential solution paths are discussed.

Assessing intrinsic and extrinsic end-of-life risk using functional SRAM wafer level testing

Extended 6 Transistors (6T) SRAM (Static Random-Access Memory) characterization is used to measure degradation while separating intrinsic from extrinsic yield and accounting for yield assessment challenges such as voltage drop and measurement variability. Separation of extrinsic yield pre- and post-stress reveals weak yield fixes and reduces HTOL (High Temperature Operating Life) failure risk.

Advanced soft fail characterization methodology for sub-28nm nanoscale SRAM yield improvement

CMOS device miniaturization and the rapidly growing demand for mobile or power-aware systems have resulted in an urgent need to lower down power supply voltage (Vdd). However, soft fails at low Vdd in SRAM Array become a major yield limiter due to process variation and VT mismatch. This paper describes an advanced characterization flow on soft fails with the combination of applying fail-specified functional memory patterns, circuit analysis and advanced PFA techniques. The flow was successfully applied in soft fail characterization for sub-28nm SRAM yield improvement.