Nuttorn Jangkrajarng

IPRAIL: intellectual property reuse-based analog IC layout automation

This paper presents a computer-aided design tool, IPRAIL, which automatically retargets existing analog layouts for technology migration and new design specifications. The reuse-based methodology adopted in IPRAIL utilizes expert designer knowledge embedded in analog layouts. IPRAIL automatically extracts analog layout intellectual properties as templates, incorporates new technology design rules and device sizes, and generates fully functional layouts. This is illustrated by retargeting two practical operational amplifier layouts from the TSMC 0.25 µm CMOS process to the TSMC 0.18 µm CMOS process. While manual re-design is known to take days to weeks, IPRAIL only takes minutes and achieves comparable circuit performances.

Parasitic-Aware Optimization and Retargeting of Analog Layouts: A Symbolic-Template Approach

Layout parasitics can significantly affect the performance of analog integrated circuits (ICs). In this paper, a systematic method of optimizing an existing analog layout considering parasitics is presented for technology migration and performance retargeting. This method represents the locations of layout rectangle edges as variables and extracts circuit and layout integrity such as device symmetry, matching, and design rules as constraints. To ensure the desired circuit performance, bounds of layout parasitics are determined first. These bounds are used to constrain the layout geometries while retargeting existing high-quality layouts across technologies and specification sets. The problem is then solved by a graph-based algorithm combined with nonlinear optimization. The proposed method has been implemented in a parasitic-aware automatic layout optimization and retargeting tool (intellectual property reuse-based analog IC layout). Its efficiency and effectiveness are demonstrated by successfully retargeting operational amplifiers within 1 min of CPU time.

Multilevel symmetry-constraint generation for retargeting large analog layouts

The strong impact of layout intricacies on analog-circuit performance poses great challenges to analog layout automation. Recently, template-based methods have been shown to be effective in reuse-centric layout automation for CMOS analog blocks such as operational amplifiers. The layout-retargeting method first creates a template by extracting a set of constraints from an existing layout representation. From this template, new layouts are then generated corresponding to new technology processes and new device specifications. For large analog layouts, however, this method results in an unmanageable template due to a tremendous increase in the number of constraints, especially those emerging from layout symmetries. In this paper, we present a new method of multilevel symmetry-constraint generation by utilizing the inherent circuit structure and hierarchy information from the extracted netlist. The method has been implemented in a layout-retargeting system called Intellectual Property Reuse-based Analog IC Layout (IPRAIL) and demonstrated 18 times reduction in the number of symmetry constraints required for retargeting an analog-to-digital converter layout. This enables our retargeting engine to successfully handle the complexities associated with large analog layouts. While manual relayout is known to take weeks, our layout-retargeting tool generates the target layout in hours and achieves comparable electrical performance

Correct-by-construction layout-centric retargeting of large analog designs

Aggressive design cycles in the semiconductor industry demand a design-reuse principle for analog circuits. The strong impact of layout intricacies on analog circuit performance necessitates design reuse with special focus on layout aspects. This paper presents a computer-aided design tool and the methodology for a layout-centric reuse of large analog intellectual-property blocks. From an existing layout representation, an analog circuit is retargeted to different processes and performances; the corresponding correct-by-construction layouts are generated automatically and have performances comparable to manually crafled layouts. The tool and the methodology are validated on large analog intellectual-properly blocks. While manual re-design and re-layout is known to take weeks: to months, our *use tool-suite achieves comparable performance in hours.

Hierarchical extraction and verification of symmetry constraints for analog layout automation

Device matching and layout symmetry are of utmost importance to high performance analog and RF circuits. In this paper, we present HiLSD, the first CAD tool for the automatic detection of layout symmetry between two or more devices in a hierarchical manner. HiLSD first extracts the circuit structure from the layout, then applies an efficient pattern-matching algorithm to find all the subcircuits automatically, and finally detects layout symmetry on the portion of the layout that corresponds to extracted subcircuit instances. On a set of practical analog layouts, HiLSD is demonstrated to be much more efficient than direct symmetry detection on a flattened layout. Results from applying HiLSD to automatic analog layout retargeting for technology migration and new specifications are also described.

Automatic analog layout retargeting for new processes and device sizes

This paper presents an automatic analog layout resizing tool that can generate a new layout incorporating the target technology process and the target transistor sizes. The tool automatically preserves the analog layout integrity by extracting layout symmetry and matching, and then solving the constrained layout generation problem using a combined linear programming and graph-theoretic approach. The tool has been applied successfully to integrate specified transistor sizes and to migrate layouts for various analog designs from TSMC 0.25 /spl mu/m CMOS to TSMC 0.18 /spl mu/m CMOS process with comparable performances to re-design.

Multiple specifications radio-frequency integrated circuit design with automatic template-driven layout retargeting

This paper presents an automatic layout retargeting tool that generates analog and RF layouts incorporating new device sizes and geometries based on new circuit specifications. A graph-based symbolic template is automatically constructed from a practical layout such that expert designer embedded in the layout is preserved. The template can be solved for multiple layouts based on different device sizes and geometries, satisfying several different specifications. Symmetry conservation and passive device modification are also embedded in the tool. The retargeting tool is demonstrated on a voltage controlled oscillator to generate three layouts with different target goals. While manual re-design is known to take days to finish, the automatic layout retargeting tool takes a few hours to generate a reusable template and takes minutes to generate comparable layouts.

Automatic device layout generation for analog layout retargeting

This paper presents a technique for automatic active device layout generation and insertion incorporated in a layout retargeting tool-suite for analog integrated circuits. While the use of a graph-based symbolic template in the retargeting tool maintains the overall layout topology, layout symmetries, and embedded expertise of the designers, the device generator allows further optimization of active devices in terms of device width, length, and finger variables through template modification. Combining the device layout generator with a design-space exploration engine that searches for optimal sets of design variables satisfying performance requirements, a new automatic design reuse methodology is presented. Multiple high quality analog circuits corresponding to different target specifications are synthesized in less than an hour, and their layouts with different device sizes and structures are generated in less than a minute of CPU time.

A high-throughput low-power fully parallel 1024-bit 1/2-rate low density parity check code decoder in 3-dimensional integrated circuits

A 1024-bit, 1/2-rate fully parallel low-density parity-check (LDPC) code decoder has been designed and implemented using a three-dimensional (3D) 0.18μm fully depleted silicon-on-insulator (FDSOI) CMOS technology based on wafer bonding. The taped-out 3D decoder with about 8M transistors was simulated to have a high throughput of 2Gb/s and a low power consumption of only 430mW using 6.4μm by 6.3μm of die area. The 3D implementation is estimated to offer more than 10x power-delay-area product improvement over its corresponding 2D implementation. This first large-scale 3D ASIC with fine-grain (5μm) vertical interconnects is made possible by jointly developing a complete automated 3D design flow from a commercial 2-D design flow combined with the needed 3D-design point tools.

Implementing a 2-Gbs 1024-bit ½-rate low-density parity-check code decoder in three-dimensional integrated circuits

A 1024-bit, 1/2-rate fully parallel low-density parity-check (LDPC) code decoder has been designed and implemented using a three-dimensional (3D) 0.18 mum fully depleted silicon-on-insulator (FDSOI) CMOS technology based on wafer bonding. The 3D-IC decoder was implemented with about 8M transistors, placed on three tiers, each with one active layer and three metal layers, using 6.9 mm by 7.0 mm of die area. It was simulated to have a 2 Gbps throughput, and consume only 260 mW. This first large-scale 3D application-specific integrated circuit (ASIC) with fine-grain (5mum) vertical interconnects is made possible by jointly developing a complete automated 3D design flow from a commercial 2-D design flow combined with the needed 3D-design tools. The 3D implementation is estimated to offer more than 10 xpower-delay-area product improvement over its corresponding 2D implementation. The work demonstrated the benefits of fine-grain 3D integration for interconnect-heavy very-large-scale digital ASIC implementation.