C.-J. Richard Shi

IPRAIL: intellectual property reuse-based analog IC layout automation

This paper presents a computer-aided design tool, IPRAIL, which automatically retargets existing analog layouts for technology migration and new design specifications. The reuse-based methodology adopted in IPRAIL utilizes expert designer knowledge embedded in analog layouts. IPRAIL automatically extracts analog layout intellectual properties as templates, incorporates new technology design rules and device sizes, and generates fully functional layouts. This is illustrated by retargeting two practical operational amplifier layouts from the TSMC 0.25 µm CMOS process to the TSMC 0.18 µm CMOS process. While manual re-design is known to take days to weeks, IPRAIL only takes minutes and achieves comparable circuit performances.

VHDL-AMS based modeling and simulation of mixed-technology microsystems: a tutorial

This tutorial paper describes different approaches to modeling and simulation of mixed-technology microsystems that consist of electrical circuits connected to subsystems described by partial differential equations (PDEs), which is a typical situation in many modern integrated circuits and systems. We target this paper towards the audience use of VHDL-AMS (a hardware description language suitable for modeling and simulation of such systems). We describe existing approaches to modeling such systems and present three examples accompanied by their VHDL-AMS implementations and simulation results.

Automatic device layout generation for analog layout retargeting

This paper presents a technique for automatic active device layout generation and insertion incorporated in a layout retargeting tool-suite for analog integrated circuits. While the use of a graph-based symbolic template in the retargeting tool maintains the overall layout topology, layout symmetries, and embedded expertise of the designers, the device generator allows further optimization of active devices in terms of device width, length, and finger variables through template modification. Combining the device layout generator with a design-space exploration engine that searches for optimal sets of design variables satisfying performance requirements, a new automatic design reuse methodology is presented. Multiple high quality analog circuits corresponding to different target specifications are synthesized in less than an hour, and their layouts with different device sizes and structures are generated in less than a minute of CPU time.

Balanced multi-level multi-way partitioning of analog integrated circuits for hierarchical symbolic analysis

This paper considers the problem of partitioning analog integrated circuits for hierarchical symbolic analysis based on determinant decision diagrams (DDDs). The objective is to use DDDs with the minimum number of vertices to represent all the symbolic expressions. We show that the problem can be formulated as that of multi-level multi-way hyper graph partitioning with balance constraints, and be solved in two phases by connectivity-oriented initial clustering and iterative improvement. Our new contribution consists of a fast and effective heuristic for constructing a balanced initial partition, a potential gain formulae that can be computed efficiently, and a multiple-vertex moving strategy for relaxing and enforcing balance constraints. The proposed algorithm has been implemented and applied to symbolic analysis of several practical analog integrated circuits. Experimental results are described and compared to the contour tableau method of Sangiovanni-Vincentelli, Chen and Chua, and the SCAPP algorithm of Hassoun and Lin. The resulting hierarchical symbolic analyzer outperforms SPICE in numerical evaluations for a number of large analog circuits.

A 10-bit 50-MS/s SAR ADC with 1 fJ/Conversion in 14 nm SOI FinFET CMOS

Abstract A 10-bit Successive Approximation Register (SAR) Analog to Digital Converter (ADC) was implemented in a 14 nm SOI FinFET CMOS technology, achieving 59.59 dB SNDR at 50 MS/s while consuming 41.3 µW power. Several techniques were used to increase the energy efficiency while ensuring the linearity. First, a segmented architecture with a 5-bit coarse ADC and an 11-bit fine ADC was used. The aligned Switching with Skip (ASS) method was used to generate the five MSBs of the fine ADC from the computed coarse ADC bits, saving 58% switching power compared with non-segmented architecture with merged capacitor switching (MCS) method. Second, VCM-based MCS scheme is used for SAR bit resolving, saving 85.72% switching power compared with traditional SAR switching. Third, the dual supply mode with analog at 0.8 V and digital at 0.4 V was used. This reduces the total digital logic power consumption by 23% comparing with that using the single supply at 0.8 V. The differential architecture was used to minimize the common mode non-idealities. The proposed ADC has been implemented in a 14 nm SOI FinFET technology and achieved a peak Figure of Merit (FoM) of 1.07 fJ/Conversion-step with simulation results.

Circuit level modeling and simulation of mixed-technology systems

The goal of this paper is to describe a methodology for circuit level modeling and simulation of mixed-technology systems, which fits into a standard electronic design flow and allows one to model and simulate such systems in a standard circuit simulator. The basis for the methodology is the use of the model compiler that allows one to compile models written in high-level behavioral description language and make them available to a standard circuit simulator. For demonstration purposes, we consider two mixed-technology examples: an optoelectronic example (a laser diode circuit) and a thermo-electronic example (thermally coupled MOS inverter). We use model compiler MCAST developed in our group to compile VHDL-AMS models and make them available to SPICE circuit simulator. Our results demonstrate that model compiler technology allows one to perform simulation of mixed-technology systems in a circuit simulator. The methodology described here is general and can be used with various model compilers and circuit simulators, as long as good mathematical models for mixed-technology devices are available.

CrtSmile: a CAD tool for CMOS RF transistor substrate modeling incorporating layout effects

This paper presents a new CAD tool CrtSmile, which automatically incorporates transistor layout effects for CMOS RF transistor modeling with an emphasis on substrate resistance extraction. The RF transistor layouts in the CIF/GDSII format are used to generate a layout dependent substrate model that can be included as a subcircuit with the BSIM3 device model. To support multi-finger RF transistor layout/bulk recognition, a pattern based layout extraction method is presented. CrtSmile incorporates a scalable substrate model for multi-finger transistors, which is dependent on transistor layout/bulk patterns and geometric layout information, such as the number of gate fingers, finger width, channel length, and bulk contact locations. This model is simple to extract and gives good agreement with the measured data for a 0.35μm CMOS process. A low noise amplifier design is evaluated with the new layout dependent substrate model and the proposed tool, showing the importance of CMOS RF transistor layout on substrate resistance modeling.