O. Cueto

Phase change memory as synapse for ultra-dense neuromorphic systems: Application to complex visual pattern extraction

We demonstrate a unique energy efficient methodology to use Phase Change Memory (PCM) as synapse in ultra-dense large scale neuromorphic systems. PCM devices with different chalcogenide materials were characterized to demonstrate synaptic behavior. Multi-physical simulations were used to interpret the results. We propose special circuit architecture (“the 2-PCM synapse”), read, write, and reset programming schemes suitable for the use of PCM in neural networks. A versatile behavioral model of PCM which can be used for simulating large scale neural systems is introduced. First demonstration of complex visual pattern extraction from real world data using PCM synapses in a 2-layer spiking neural network (SNN) is shown. System power analysis for different scaled PCM technologies is also provided.

Electrical Behavior of Phase-Change Memory Cells Based on GeTe

In this letter, we present a study on the electrical behavior of phase-change memories (PCMs) based on a GeTe active material. GeTe PCMs show, first, extremely rapid SET operation (yielding a gain of more than one decade in energy per bit with respect to standard GST PCMs), second, robust cycling, up to 1 × 105, with 30-ns SET and RESET stress time, and third, a better retention behavior at high temperature with respect to GST PCMs. These results, obtained on single cells, suggest GeTe as a promising alternative material to standard GST to improve PCM performance and reliability.

Physical aspects of low power synapses based on phase change memory devices

In this work, we demonstrate how phase change memory (PCM) devices can be used to emulate biologically inspired synaptic functions in particular, potentiation and depression, important for implementing neuromorphic hardware. PCM devices with different chalcogenide materials are fabricated and characterized. The asymmetry between the potentiation and depression behaviors of the PCM is stressed. Detailed multi-physical simulations are performed to study the underlying physics of the synaptic behavior of PCM. A versatile behavioral model and a multi-level circuit-compatible model are developed for system and circuit-level neuromorphic simulations. We propose a unique low-power methodology named the 2-PCM Synapse, to use PCM devices as synapses in large scale neuromorphic systems. To show the strength of our proposed solution, we efficiently simulated fully connected feed-forward spiking neural network capable of complex visual pattern extraction from real world data.

Investigation of the potentialities of Vertical Resistive RAM (VRRAM) for neuromorphic applications

Combining Resistive RAM concept with Vertical NAND technology and design, Vertical RRAM (VRRAM) was recently proposed as a cost-effective and extensible technology for future mass data storage applications [1]. 3D RRAM based neural networks were also proposed to emulate the potentiation and depression of a synapse [2], but more complex circuits were not discussed. In previous works [3-4], various RRAM based neuromorphic circuits were proposed and investigated, using planar devices.

Scalability of split-gate charge trap memories down to 20nm for low-power embedded memories

In this work, split-gate charge trap memories with electrical gate length down to 20nm are presented for the 1^st time. Silicon nanocristals (Si-ncs), or silicon nitride (Si<inf>3</inf>N<inf>4</inf>) and hybrid Sinc/SiN based split-gate memories, with SiO<inf>2</inf> or Al<inf>2</inf>O<inf>3</inf> control dielectrics, are compared in terms of program erase and retention. Then, the scalability of split-gate charge trap memories is studied, investigating the impact of gate length reduction on the memory window, retention and consumption. The results are analyzed by means of TCAD simulations.

Investigation of the physical mechanisms governing data-retention in down to 10nm nano-trench Al 2 O 3 /CuTeGe conductive bridge RAM (CBRAM)

In this work, we present an experimental and theoretical analysis of scaled (down to 10nm) Al2O3/CuTeGe based CBRAM. We focus on the understanding of the physical mechanisms responsible for the failure of high and low resistance states at high temperature. Using a numerical model combined with ab-initio calculations, we elucidate for the 1st time at our knowledge the role of the filament morphology on the resistance instability. We demonstrate that an optimized filament shape (tuned by adjusting the operating conditions) significantly improves the memory window stability at high temperatures.

Experimental and theoretical understanding of Forming, SET and RESET operations in Conductive Bridge RAM (CBRAM) for memory stack optimization

In this paper, we deeply investigate for the 1st time at our knowledge the impact of the CBRAM memory stack on the Forming, SET and RESET operations. Kinetic Monte Carlo simulations, based on inputs from ab-initio calculations and taking into account ionic hopping and chemical reaction dynamics are used to analyse experimental results obtained on decananometric devices. We propose guidelines to optimize the CBRAM stack, targeting Forming voltage reduction, improved trade-off between SET speed and disturb immunity (time voltage dilemma) and window margin increase (RESET efficiency).

Investigation of the role of H-related defects in Al 2 O 3 blocking layer on charge-trap memory retention by atomistic simulations and device physical modelling

In this work, we use atomistic simulation, consolidated by a detailed Al2O3 physico-chemical material analysis, to investigate the origin of traps in Al2O3 (in particular, Al- or O-vacancies and H-interstitials). It is shown that the leakage currents through Al2O3 layers, with different post-deposition anneals, are strictly correlated to the H content. Then, for the first time at our knowledge, the hydrogen-based trap features estimated by quantum simulations are introduced in a TANOS device simulator. A very good agreement is obtained between model and device experimental data, allowing for a clear understanding of the role of alumina H content on the retention characteristics of charge-trap memories.

Future challenges and opportunities for heterogeneous process technology. Towards the thin films, Zero Intrinsic Variability devices, Zero Power era

Linear scaling CMOS has encountered many hurdles which request new process modules, driven mainly by the maximization of energy efficiency. Fabrication at the sub 10nm node level will request Intrinsic Variability approaching to zero. The rapid growth of mobile, multifunctional and autonomous systems is hardly demanding to reach Zero Power consumption. The solutions to integrate Thin Film based devices, architectures and systems in order to face these challenges are described.

Effect of SET temperature on data retention performances of HfO 2 -based RRAM cells

In this paper the effect of SET temperature on data-retention performances in HfO2-based RRAM has been thoroughly investigated. We demonstrated, for the first time to our knowledge, that high temperature programming (even if it has no influence on the initial resistance) has a strong effect on thermal stability of the conductive filaments. Moreover, we highlighted the impact of SET temperature also on RESET characteristics. We gathered all these experimental evidences under a simple modeling of the filament morphology, proving that the filament size might be tuned by adjusting the programming temperature. We conclude that reducing the conductive filament diameter while keeping high density of the oxygen vacancies significantly improves data retention.