Marc Bocquet

Experimental and theoretical study of electrode effects in HfO 2 based RRAM

In this work, the impact of Ti electrodes on the electrical behaviour of HfO2-based RRAM devices is conclusively clarified. To this aim, devices with Pt, TiN and Ti electrodes have been fabricated (see Fig. 1). We first provide several experiments to clearly demonstrate that switching is driven by creation-disruption of a conductive filament. Thus, the role of TiN/Ti electrodes is explained and modeled based on the presence of HfOx interfacial layer underneath the electrode. In addition, Ti is found responsible to activate bipolar switching. Moreover, it strongly reduces forming and switching voltages with respect to Pt-Pt devices. Finally, it positively impacts on retention. To support and interpret our results we provide physico-chemical measurements, electrical characterization, ab-initio calculations and modeling.

Self-consistent physical modeling of set/reset operations in unipolar resistive-switching memories

This Letter deals with a self-consistent physical model for set/reset operations involved in unipolar resistive switching memories integrating a transition metal oxide. In this model, set operation is described in terms of a local electrochemical reduction of the oxide leading to the formation of metallic conductive filaments. Beside, reset operation relies on the thermally assisted destruction of the formed metallic filaments by Joule heating effect. An excellent agreement is demonstrated with numerous published experimental data suggesting that this model can be confidently implemented into circuit simulators for design purpose.

Synchronous Non-Volatile Logic Gate Design Based on Resistive Switching Memories

Emerging non-volatile memories (NVM) based on resistive switching mechanism (RS) such as STT-MRAM, OxRRAM and CBRAM etc., are under intense R&D investigation by both academics and industries. They provide high write/read speed, low power and good endurance (e.g., > 1012) beyond mainstream NVMs, which allow them to be embedded directly with logic units for computing purpose. This integration could increase significantly the power/die area efficiency, and then overcome definitively the power/speed bottlenecks of modern VLSIs. This paper presents firstly a theoretical investigation of synchronous NV logic gates based on RS memories (RS-NVL). Special design techniques and strategies are proposed to optimize the structure according to different resistive characteristics of NVMs. To validate this study, we simulated a non-volatile full-adder (NVFA) with two types of NVMs: STT-MRAM and OxRRAM by using CMOS 40 nm design kit and compact models, which includes related physics and experimental parameters. They show interesting power, speed and area gain compared with synchronized CMOS FA while keeping good reliability.

Robust Compact Model for Bipolar Oxide-Based Resistive Switching Memories

Emerging nonvolatile memories based on resistive switching mechanisms pull intense research and development efforts from both academia and industry. Oxide-based resistive random access memories (OxRAM) gather noteworthy performances, such as fast WRITE/READ speed, low power, high endurance, and large integration density that outperform conventional flash memories. To fully explore new design concepts, such as distributed memory in logic or biomimetic architectures, robust OxRAM compact models must be developed and implemented into electrical simulators to assess performances at a circuit level. In this paper, we propose a physics-based compact model used in electrical simulator for bipolar OxRAM memories. After uncovering the theoretical background and the set of relevant physical parameters, this model is confronted to experimental electrical data. The excellent agreement with these data suggests that this model can be confidently implemented into circuit simulators for design purpose.

Resistance controllability and variability improvement in a TaOx-based resistive memory for multilevel storage application

In order to obtain reliable multilevel cell (MLC) characteristics, resistance controllability between the different resistance levels is required especially in resistive random access memory (RRAM), which is prone to resistance variability mainly due to its intrinsic random nature of defect generation and filament formation. In this study, we have thoroughly investigated the multilevel resistance variability in a TaOx-based nanoscale (<30 nm) RRAM operated in MLC mode. It is found that the resistance variability not only depends on the conductive filament size but also is a strong function of oxygen vacancy concentration in it. Based on the gained insights through experimental observations and simulation, it is suggested that forming thinner but denser conductive filament may greatly improve the temporal resistance variability even at low operation current despite the inherent stochastic nature of resistance switching process.

Bipolar ReRAM Based non-volatile flip-flops for low-power architectures

Resistive Random Access Memories (ReRAMs) fabricated in the back-end-of-line are a promising breakthrough for including permanent retention mechanisms in embedded systems. This low-cost solution opens the way to advanced power management schemes. In this paper, we propose novel design architecture of a non-volatile flip-flop based on Bipolar ReRAMs (Bi-RNVFF). Compared to state-of-the-art Data-Retention flip-flop (with Balloon latch), the proposed design is 25% smaller due to 6T structure compared to the 8T structure of Data-Retention flip-flop. Moreover, being non-volatile, the proposed architecture exhibits a zero leakage compared to a Data-Retention Flip-Flop, which consumes ~3.2μW in sleep mode (leakage) for a 10K Flip-Flop design implemented in 22nm FDSOI technology. Our simulation results show that Bi-RNVFF is a true alternative for future “Power-on, Power-off” application adding Non-Volatility without significant burdening of the existing architectures.

Thorough investigation of Si-nanocrystal memories with high-k interpoly dielectrics for sub-45nm node Flash NAND applications

In this paper we show for the 1st time that Silicon nanocrystal (Si-ncs) memories with high-k (HfO2, Al2O3 and HfAlO) interpoly dielectrics (IPD) can offer excellent behaviour in the Fowler-Nordheim regime, with great relevance for future sub-45 nm NAND memory generations. We significantly advance the state-of-the-art by showing a strict correlation between the different IPD properties and the performance obtained on memory transistors down to 90 nm gate lengths. In particular the results demonstrate that HfAlO IPDs combine the fast p/e and good 105 cycles endurance behaviour of HfO2 and the long retention of Al2O3 with no activation up to 125degC Then, in order to boost the memory window, we also integrated a hybrid Si-nc/SiN layer floating gate, with a HfAlO based IPD. It is shown that a 6V DeltaVth can be achieved, with good retention and cycling behaviours.

Investigation of the potentialities of Vertical Resistive RAM (VRRAM) for neuromorphic applications

Combining Resistive RAM concept with Vertical NAND technology and design, Vertical RRAM (VRRAM) was recently proposed as a cost-effective and extensible technology for future mass data storage applications [1]. 3D RRAM based neural networks were also proposed to emulate the potentiation and depression of a synapse [2], but more complex circuits were not discussed. In previous works [3-4], various RRAM based neuromorphic circuits were proposed and investigated, using planar devices.

Bipolar OxRRAM memory array reliability evaluation based on fault injection

In this paper, a fault injection and simulation approach is used to study effects of resistive and capacitive defects on the faulty behavior of Oxide-based Resistive Memory RAM devices (OxRRAM). During the memory operations, logical and electrical characteristics of each memory cell of an elementary array are evaluated by using a bipolar OxRRAM compact model calibrated on actual devices. Simulation results are analyzed in terms of OxRRAM electrical characteristic variations to evaluate the robustness of the memory array against injected defects, inherent to the routing circuitry.

Temperature impact (up to 200 °C) on performance and reliability of HfO 2 -based RRAMs

This paper provides an overview of the temperature impact (up to 200 °C) on the electrical behavior of oxide-based RRAM, during forming, low-field resistance reading, SET/RESET, disturb, data retention and endurance. HfO2-RRAM devices (in a 1T1R configuration) integrated in an advanced 65 nm technology are studied for this aim. We show that forming operation is strongly activated in temperature (i.e. -0.5 V per hundred Celsius degree), being much less for SET and RESET voltages (i.e. <; -0.05 V per hundred Celsius degree); disturb of HRS at fixed voltage showed to be independent of temperature; endurance up to 3.106 cycles, with optimized set of stress parameters showed no significant variation; data retention at 150 °C up to 68 days showed stable programming window, after different initial programming algorithms.