O. Paul

Process-dependent thin-film thermal conductivities for thermal CMOS MEMS

The thermal conductivities /spl kappa/ of the dielectric and conducting thin films of three commercial CMOS processes were determined in the temperature range from 120 to 400 K. The measurements were performed using micromachined heatable test structures containing the layers to be characterized. The /spl kappa/ values of thermally grown silicon oxides are reduced from bulk fused silica by roughly 20%. The /spl kappa/ of phosphosilicate and borophosphosilicate glasses are 0.94/spl plusmn/0.08 W m/sup -1/ K/sup -1/ and 1.18/spl plusmn/0.06 W m/sup -1/ K/sup -1/, respectively, at 300 K. A plasma-enhanced chemical-vapor-deposition silicon-nitride layer has a thermal conductivity of 2.23/spl plusmn/0.12 W m/sup -1/ K/sup -1/ at 300 K. This value is between published data for atmospheric-pressure CVD and low-pressure CVD nitrides. For the metal layers, we found thermal conductivities between 167 W m/sup -1/ K/sup -1/ and 206 W m/sup -1/ K/sup -1/, respectively, at 300 K, to be compared with 238 W m/sup -1/ K/sup -1/ of bulk aluminum. The temperature-dependent product /spl kappa//spl rho/ of /spl kappa/ with the electrical resistivity /spl rho/ agrees better than 8.2% between 180-400 K with that of pure bulk aluminum. The /spl kappa/ values of the polysilicon layers are between 22.4 W m/sup -1/ K/sup -1/ and 37.3 W m/sup -1/ K/sup -1/ at 300 K. They are reduced from similarly doped bulk silicon by factors of between 2.0-1.3. The observed discrepancies between thin film and bulk data demonstrate the importance of determining the process-dependent thermal conductivities of CMOS thin films.

CMOS integration of a thermal pressure sensor system

We report the integration of a CMOS thermal pressure sensor system for the range of 10/sup 2/ to 10/sup 6/ Pa. The operating principle of the sensor is based on the pressure-dependent heat transfer across the air gap separating a heat source from a heat sink. After completion of the double metal CMOS process the sensor structure is obtained by a fully CMOS-compatible sacrificial metal etching. The microsystem includes both sensor and a readout circuit. The interface circuit compensates for temperature effects and provides a bitstream at the system output representing the ambient pressure.

IC MEMS microtransducers

This invited review of the merging of MEMS and IC technology includes a summary of the current technological approaches to IC MEMS, illustrations by selected IC MEMS microtransducer demonstrators, an outline of the MEMS CAD tools SOLIDIS and ICMAT, and a critical evaluation.

Solder-bonded micromachined capacitive pressure sensors

We report the first solder-bonding of low-cost silicon absolute pressure sensors. The goal of the work is to solder a pressure sensor wafer and a CMOS wafer containing the signal conditioning circuitry together face to face under vacuum. The result is a very flat capacitive absolute pressure sensor which can be used in harsh environments for automotive, medical, barometric, and other applications. We successfully demonstrated this approach using sensor wafers with micromachined silicon membranes and CMOS wafers without signal conditioning circuitry. Solder frames surrounding the membrane are electroplated on the sensor wafer. Different solder materials such as Au/Sn and SnPb were examined. Characterization of the hermetic prototypes in a pressure chamber showed a sensitivity of 0.8 fF/mbar, in good agreement with finite (FE) element simulations. With special regard to the sensitivity of the sensor a quadratic membrane, a rectangular membrane and a square membrane with a boss, all with an area of 2.25 mm2, were compared using FE analysis. The rectangular membrane has the largest sensitivity.

Test structures to measure the Seebeck coefficient of CMOS IC polysilicon

We report on two thermal characterization structures to measure the Seebeck coefficient /spl alpha/ of CMOS IC polysilicon thin films relevant for integrated thermal microtransducers. The test structures were fabricated using the commercial 1.2 /spl mu/m CMOS process of Austria Mikro Systeme (AMS). The fabrication of the first structure relies on silicon micromachining. In contrast the second, planar, structure is ready for measurement after IC fabrication. The temperature dependent /spl alpha/ of the two polysilicon layers of the AMS process were measured with both characterization devices. The agreement between the two data sets validates the new structure.

Ageing behavior of polysilicon heaters for CMOS microstructures operated at temperatures up to 1200 K

We report the operation of micro test structures at temperatures up to 1200 K. The structures realized by a standard CMOS process consist of dielectric membranes which are heated resistively by an integrated, degenerately n-doped polysilicon heater. The heater itself serves as temperature monitor and as object of interest to characterize the ageing behavior of polysilicon. The structures are cycled thermally to temperatures up to 1200 K by increasing the electrical heating power stepwise to 124 mW. Depending on the cooling rate of the thermal cycles, the resistance of the heater can reversibly be changed between +33% (cooling rate 0.02 K/s) and -17% (cooling rate 12.1 K/s) of its initial value. During the constant power steps of the heating/cooling cycles exponential resistance changes vs. time with time constants in the range of seconds to a few minutes are observed.

Thermoelectric test structures to measure the heat capacity of CMOS layer sandwiches

We report a novel thermal characterization microstructure to measure the heat capacity of CMOS IC layer sandwiches. This parameter is relevant, e.g., for the dynamic response of thermal CMOS microtransducers. The test structures were fabricated using the commercial 2 /spl mu/m low voltage CMOS process of EM Microelectronic Marin, Switzerland, followed by maskless micromachining. The Seebeck coefficient of gate polysilicon against the lower CMOS metal is used to monitor the propagation of heat waves along the microstructure. At 300 K, volumetric heat capacities of 1.82/spl plusmn/0.12/spl times/10/sup 6/ Jm/sup -3/ K/sup -1/ and 1.66/spl plusmn/0.06/spl times/10/sup 6/ Jm/sup -3/ K/sup -1/ were obtained, respectively, for the passivation sandwich and the full sandwich of CMOS dielectrics including the lower metal and polysilicon.

Test structures to measure the heat capacity of CMOS layer sandwiches

We report novel thermal characterization microstructures to measure the heat capacity c of CMOS IC layer sandwiches. This parameter is relevant, e.g., for the dynamic response of thermal CMOS microtransducers. The test structures were fabricated using the commercial 2 /spl mu/m low voltage CMOS process of EM Microelectronic Marin, Switzerland, followed by maskless micromachining. At 300 K, volumetric heat capacities of 1.74/spl plusmn/0.13/spl times/10/sup 6/ Jm/sup -3/ K/sup -1/ and 2.23/spl plusmn/1.87/spl times/ 10/sup 6/ Jm/sup -3/ K/sup -1/ for the sandwich of CMOS dielectrics and for the lower CMOS metal, respectively, were obtained.