Ockgoo Lee

A Cascode Feedback Bias Technique for Linear CMOS Power Amplifiers in a Multistage Cascode Topology

A novel feedback bias technique for a multistage cascode topology is developed to improve the linearity and reliability of power amplifiers (PAs). Due to the large parasitic capacitance and low substrate resistivity of CMOS technology, signal swings are coupled between the ports of transistors. The proposed method utilized the RF leakage signals at the gate of common-gate (CG) transistor in a cascode topology for employing negative feedback, which not only enhances the linearity of the PA, but also alleviates the voltage stress between the gate and the drain of the CG device in a cascode topology from 4.5 to 1.9 V. This technique requires no additional components or space and is easily applicable to the multistage cascode topology, which is one of the most popular structures of CMOS PA designs. In order to prove the concept, a 1.95-GHz fully integrated linear PA was implemented in a 0.18- μm CMOS technology. With a 3.4-V power supply, the PA transmits a saturated output power of 26 dBm with a power-added efficiency (PAE) of 46.4%, and a linear output power of 23.5 dBm with a PAE of 40% using a 3 GPP WCDMA modulated signal. The PA occupies 1.60 × 0.52 mm2. This PA demonstrates the potential of the highly efficient CMOS PA design approach for wireless communication standards.

A highly efficient WLAN CMOS PA with two-winding and single-winding combined transformer

In this paper, a fully integrated high-efficiency linear CMOS power amplifier (PA) is developed for 802.11g WLAN applications with the proposed power combining transformer. In comparison with conventional power combining transformers, the proposed power combining transformer can offer high-efficiency performances with a smaller die size. The fabricated two-stage PA using a 65nm CMOS technology achieves a saturated output power of 26.7 dBm with a drain efficiency (DE) of 47.7% at 2.48 GHz. The PA is tested with 54Mbps WLAN 802.11g signal and it meets the stringent error vector magnitude (EVM) and spectral mask requirements at a 20.13-dBm output power with a DE of 21.4%.

A 2×2 MIMO multi-band RF transceiver and power amplifier for compact LTE small cell base station

We present a fully integrated 2×2 MIMO CMOS LTE RF transceiver along with multi-band InGaP/GaAs HBT power amplifiers for LTE-A small cell (femtocell) base stations. The transceiver features highly integrated LNAs and drive amplifiers with 24 individual RF I/O pins. The multi-band PAs achieves ACLR <-45dBc at 25dBm with PAE >38% at 33dBm by employing a third-order intermodulation distortion (IMD3) canceling techniques. The presented SiP composed of proposed radio and PAs shows plenty of margins in radio conformal test of femtocell base station using a commercial modem.

A Linear InGaP/GaAs HBT Power Amplifier Using Parallel-Combined Transistors With IMD3 Cancellation

In this letter, we present a linear InGaP/GaAs HBT power amplifier (PA) with parallel-combined transistors for small-cell applications. Ballast resistors with bypass resistors and capacitors are employed in parallel-combined transistors. When the resistors and capacitors are set to appropriate values, IMD3 components of the parallel-combined transistors are found to be out of phase with each other by 180° and are canceled out at the output. The experimental results show that the proposed HBT PA with parallel-combined transistors produces a saturated output power of 33.5 dBm at 0.88 GHz, with a power-added efficiency (PAE) of 46.1% at a 5-V supply voltage. To validate the effectiveness of the proposed HBT PA for linearity improvement, the implemented PA is also tested with a long-term evolution (LTE) signal (8.1-dB PAPR with 10-MHz bandwidth). The proposed PA achieves an adjacent channel leakage ratio (ACLR) below -45 dBc at an average power of 25.6 dBm with a PAE of 18.8% without applying predistortion.

A High-Efficiency CMOS Power Amplifier Using 2:2 Output Transformer for 802.11n WLAN Applications

A fully integrated high-efficiency linear CMOS power amplifier (PA) is developed for 802.11n WLAN applications using the 65-nm standard CMOS technology. The transformer topology is investigated to obtain a high-efficiency and high-linearity performance. By adopting a 2:2 output transformer, an optimum impedance is provided to the PA core. Besides, a LC harmonic control block is added to reduce the AM-to-AM/AM-to-PM distortions. The CMOS PA produces a saturated power of 26.1 dBm with a peak power-added efficiency (PAE) of 38.2%. The PA is tested using an 802.11n signal, and it satisfies the stringent error vector magnitude (EVM) and mask requirements. It achieves ?28-dB EVM at an output power of 18.6 dBm with a PAE of 14.7%.

A 5.5-GHz CMOS power amplifier using parallel-combined transistors with cascode adaptive biasing for WLAN applications

This paper presents a fully integrated power amplifier (PA) using parallel-combined transistors with a cascode adaptive biasing, implemented in a standard 65 nm CMOS process. The parallel-combined transistors in the common-source stage linearizes the effective gm. In addition, adaptive bias circuits are applied to both the common-source and common-gate stages to provide optimum operation conditions to each transistor, according to the output power variations. When the fully integrated PA was tested with a modulation and coding scheme 7 (MCS7) 802.11n signal, it meets a −28 dB error vector magnitude and spectral mask requirements at 18.4 dBm of average output power, with a power-added efficiency of 13.1%.

A Fully Integrated Dual-Band WLP CMOS Power Amplifier for 802.11n WLAN Applications

A fully integrated dual-band CMOS power amplifier (PA) is developed for 802.11n WLAN applications using wafer-level package (WLP) technology. This paper presents a detailed design for the optimal impedance of dual-band PA (2 GHz/5 GHz PA) output transformers with low loss, which is provided by using 2:2 and 2:1 output transformers for the 2 GHz PA and the 5 GHz PA, respectively. In addition, several design issues in the dual-band PA design using WLP technology are addressed, and a design method is proposed. All considerations for the design of dual-band WLP PA are fully reflected in the design procedure. The 2 GHz WLP CMOS PA produces a saturated power of 26.3 dBm with a peak power-added efficiency (PAE) of 32.9%. The 5 GHz WLP CMOS PA produces a saturated power of 24.7 dBm with a PAE of 22.2%. The PA is tested using an 802.11n signal, which satisfies the stringent error vector magnitude (EVM) and mask requirements. It achieved an EVM of -28 dB at an output power of 19.5 dBm with a PAE of 13.1% at 2.45 GHz and an EVM of -28 dB at an output power of 18.1 dBm with a PAE of 8.9% at 5.8 GHz.

A Fully Integrated Dual-Mode CMOS Power Amplifier With an Autotransformer-Based Parallel Combining Transformer

This letter presents a fully integrated dual-mode power amplifier (PA) with an autotransformer-based parallel combining transformer (ABPCT), fabricated with a standard 40-nm CMOS process. In comparison with a parallel combining transformer, the proposed ABPCT can offer high-efficiency performance in both high-power (HP) and low-power (LP) modes, and does so with a compact die area. With an 802.11g signal (64-QAM 54 Mbps) of 20-MHz channel bandwidth, the fully integrated dual-mode PA achieves 19.7 and 15.7 dBm average output powers with PAEs of 17.1% and 13%, in HP and LP modes, respectively, while satisfying a −25 dB error vector magnitude and spectral mask requirements. Operating the PA in the LP mode can save more than 40% of the current consumption at a 10-dBm average output power when compared with that in the HP mode.

A +12-dBm OIP3 60-GHz RF Downconversion Mixer With an Output-Matching, Noise- and Distortion-Canceling Active Balun for 5G Applications

A CMOS millimeter-wave (mmWave) downconversion mixer with a local-oscillator (LO) buffer is proposed for wireless Gb/s data-transfer enabling systems, such as 5G systems. To obtain high linearity at low supply voltages, the proposed mmWave downconversion mixer adopts an on-chip transformer-based topology. In order to achieve differential to single-ended conversion and IF output matching, while maintaining a high linearity performance, the proposed mmWave downconversion mixer incorporates an active balun with common-source and common-drain configurations employing common-mode noise and third-order intermodulation distortion cancellations. The proposed downconversion mixer with active balun and LO buffer was implemented using a 65-nm CMOS process and it draws 18 mA from a 1 V supply voltage. It demonstrates a gain greater than 5.6 dB, noise figure less than 10.9 dB, and third-order output intercept point more than 12.4 dBm, in the band from 57 to 66 GHz.

A Fully Differential RC Calibrator for Accurate Cut-off Frequency of a Programmable Channel Selection Filter

A fully differential RC calibrator for accurate cut-off frequency of a programmable channel selection filter is proposed. The proposed RC calibrator consists of an RC timer, clock generator, synchronous counter, digital comparator, and control block. To verify the proposed RC calibrator, a six-order Chebyshev programmable low-pass filter with adjustable 3 dB cut-off frequency, which is controlled by the proposed RC calibrator, was implemented in a 0.18-mm CMOS technology. The channel selection filter with the proposed RC calibrator draws 1.8 mA from a 1.8 V supply voltage and the measured 3 dB cut-off frequencies of the channel selection LPF is controlled accurately by the RC calibrator.