Ilku Nam

A Wideband CMOS Low Noise Amplifier Employing Noise and IM2 Distortion Cancellation for a Digital TV Tuner

A wideband CMOS low noise amplifier (LNA) with single-ended input and output employing noise and IM2 distortion cancellation for a digital terrestrial and cable TV tuner is presented. By adopting a noise canceling structure combining a common source amplifier and a common gate amplifier by current amplification, the LNA obtains a low noise figure and high IIP3. IIP2 as well as IIP3 of the LNA is important in broadband systems, especially digital terrestrial and cable TV applications. Accordingly, in order to overcome the poor IIP2 performance of conventional LNAs with single-ended input and output and avoid the use of external and bulky passive transformers along with high sensitivity, an IM2 distortion cancellation technique exploiting the complementary RF performance of NMOS and PMOS while retaining thermal noise canceling is adopted in the LNA. The proposed LNA is implemented in a 0.18 mum CMOS process and achieves a power gain of 14 dB, an average noise figure of 3 dB, an IIP3 of 3 dBm, an IIP2 of 44 dBm at maximum gain, and S11 of under -9 dB in a frequency range from 50 MHz to 880 MHz. The power consumption is 34.8 mW at 2.2 V and the chip area is 0.16 mm2.

The impact of semiconductor technology scaling on CMOS RF and digital circuits for wireless application

The impact of CMOS technology scaling on the various radio frequency (RF) circuit components such as active, passive and digital circuits is presented. Firstly, the impact of technology scaling on the noise and linearity of the low-noise amplifier (LNA) is thoroughly analyzed. Then two new circuits, i.e., CMOS complementary parallel push-pull (CCPP) circuit and vertical-NPN (V-NPN) circuit for direct-conversion receiver (DCR), are introduced. In CCPP, the high RF performance of pMOS comparable to nMOS provides single ended differential RF signal processing capability without the use of a bulky balun. The use of parasitic V-NPN bipolar transistor, available in triple well CMOS technology, has shown to provide more than an order of magnitude improvement in 1/f noise and dc offset related problems, which have been the bottleneck for CMOS single chip integration. Then CMOS technology scaling for various passive device performances such as the inductor, varactor, MIM capacitor, and switched capacitor, is discussed. Both the forward scaling of the active devices and the inverse scaling of interconnection layer, i.e., more interconnection layers with effectively thicker total dielectric and metal layers, provide very favorable scenario for all passive devices. Finally, the impact of CMOS scaling on the various digital circuits is introduced, taking the digital modem blocks, the various digital calibration circuits, the switching RF power amplifier, and eventually the software defined radio, as examples.

A 32-KB Standard CMOS Antifuse One-Time Programmable ROM Embedded in a 16-bit Microcontroller

A 32-KB standard CMOS antifuse one-time programmable (OTP) ROM embedded in a 16-bit microcontroller as its program memory is designed and implemented in 0.18-mum standard CMOS technology. The proposed 32-KB OTP ROM cell array consists of 4.2 mum2 three-transistor (3T) OTP cells where each cell utilizes a thin gate-oxide antifuse, a high-voltage blocking transistor, and an access transistor, which are all compatible with standard CMOS process. In order for high density implementation, the size of the 3T cell has been reduced by 80% in comparison to previous work. The fabricated total chip size, including 32-KB OTP ROM, which can be programmed via external I 2C master device such as universal I2C serial EEPROM programmer, 16-bit microcontroller with 16-KB program SRAM and 8-KB data SRAM, peripheral circuits to interface other system building blocks, and bonding pads, is 9.9 mm2. This paper describes the cell, design, and implementation of high-density CMOS OTP ROM, and shows its promising possibilities in embedded applications

A CMOS Active Feedback Balun-LNA With High IIP2 for Wideband Digital TV Receivers

A wideband active feedback single-to-differential (S-to-D) low-noise amplifier (LNA) for digital TV (DTV) tuners composed of a S-to-D converter, a voltage combiner, and a negative feedback network is proposed to achieve low noise as well as to improve the linearity performances (IIP2 and IIP3) simultaneously. By feeding the single-ended output of the voltage combiner, which is used for combining the differential output of the S-to-D converter, to the input of the LNA through the feedback network, a wideband S-to-D LNA exploiting negative feedback is implemented. The differential mode operation of the voltage combiner reduces the second-order nonlinearity feedback, allowing us to improve both the IIP3 and IIP2 of the LNA at the same time. Two LNA design examples are presented to demonstrate usefulness of the proposed approach. The LNA I, by adopting a common source (CS) amplifier with a common gate, common source (CGCS) balun load as the S-to-D converter, is able to achieve a high gain and a low noise figure (NF) by increasing the loop gain. The LNA II using the differential amplifier with the ac-grounded second input terminal is designed for robust IIP2 to PVT variations.

CMOS RF amplifier and mixer circuits utilizing complementary Characteristics of parallel combined NMOS and PMOS devices

Design and chip fabrication results for complementary RF circuit topologies that utilize the complementary RF characteristics of both NMOS and PMOS field-effect-transistor devices combined in parallel way are reported, which can inherently provide single-ended differential signal-processing capability, requiring neither baluns, nor differential signal generating/combining circuits. The proposed complementary CMOS parallel push-pull (CCPP) amplifier gives an order of magnitude improvement in IP/sub 2/ than an NMOS common-source amplifier and single-balanced CCPP resistive mixer, which functions effectively as a double-balanced one, provides more than an order of magnitude better linearity in IP/sub 2/, and similar order of magnitude better local oscillator (LO)-IF and LO-RF isolations than NMOS counterparts.

A 2.4-GHz Low-Power Low-IF Receiver and Direct-Conversion Transmitter in 0.18-

In this paper, a low-power low-IF receiver and a direct-conversion transmitter (DCT) suitable for the IEEE standard 802.15.4 radio system at the 2.4-GHz band are presented in 0.18-mum deep n-well CMOS technology. By using vertical NPN (V-NPN) bipolar junction transistors in the baseband analog circuits of the low-IF receiver, the image rejection performance is improved and the power consumption is reduced. In addition, by applying the V-NPN current mirrored technique in a DCT, the carrier leakage is reduced and the linearity performance is improved. The receiver has 10 dB of noise figure, -15 dBm of third-order input intercept point, and 35 dBc of image rejection. The transmitter has more than -2 dBm of transmit output power, -35 dBc of local oscillator leakage, and -46 dBc of the transmit third harmonic component. The receiver and transmitter dissipate 6 and 9 mA from a 1.8-V supply, respectively

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The electrical characteristics of the parasitic vertical NPN (V-NPN) BJT available in deep n-well 0.18-/spl mu/m CMOS technology are presented. It has about 20 of current gain, 7 V of collector-emitter breakdown voltage, 20 V of collector-base breakdown voltage, 40 V of Early voltage, about 2 GHz of cutoff frequency, and about 4 GHz of maximum oscillation frequency at room temperature. The corner frequency of 1/f noise is lower than 4 kHz at 0.5 mA of collector current. The double-balanced RF mixer using V-NPN shows almost free 1/f noise as well as an order of magnitude smaller dc offset compared with CMOS circuit and 12 dB flat gain almost up to the cutoff frequency. The V-NPN operational amplifier for baseband analog circuits has higher voltage gain and better input noise and input offset performance than the CMOS ones at the identical current. These circuits using V-NPN provide the possibility of high-performance direct conversion receiver implementation in CMOS technology.

CMOS for IEEE 802.15.4 WPAN Applications

A CMOS broadband differential low noise amplifier (LNA) employing noise and third order intermodulation (IM3) distortion cancellation has been designed using a 0.13 μm CMOS process for mobile TV tuners. By combining a common gate amplifier with a common source amplifier through a current mirror, a high gain due to the additional current amplification and a low noise figure (NF) due to the thermal noise cancellation can be achieved with low power consumption without degrading the input matching. To improve the linearity with low power consumption, a multiple gated transistor technique for canceling the IM3 distortion is adopted. The proposed LNA has a maximum gain of 14.5 dB, an averaged NF of 3.6 dB, an IIP3 of 3 dBm, an IIP2 of 38 dBm, and an |Sn11| lower than -9 dB in a frequency range from 72 to 850 MHz. The power consumption is 9.6 mW at a 1.2 V supply voltage and the chip area is 0.08 mm2.

High-performance RF mixer and operational amplifier BiCMOS circuits using parasitic vertical bipolar transistor in CMOS technology

RF characteristics of the parasitic vertical NPN bipolar junction transistor (BJT) available in 0.18 /spl mu/m foundry deep n-well CMOS technology are reported for the first time. The experimental results show that the vertical NPN BJT has about 20 of current gain, 7 V of collector-emitter breakdown voltage, 20 V of collector-base breakdown voltage, 40 V of early voltage, 2.3 GHz of cutoff frequency, and 3.5 GHz of maximum oscillation frequency at room temperature. The corner frequency of flicker noise is lower than 4 kHz at 0.5 mA. Double balanced RF mixer using V-NPN shows almost free 1/f noise as well as order of magnitude smaller DC offset with other characteristics comparable with CMOS one and 12 dB flat up to the cutoff frequency, opening the possibility of high performance direct conversion receiver implementation in CMOS technology.

A Low Power Broadband Differential Low Noise Amplifier Employing Noise and IM3 Distortion Cancellation for Mobile Broadcast Receivers

A wideband active feedback single-to-differential (S-to-D) LNA composed of a S-to-D converter, a voltage combiner, and a negative feedback network is proposed. By feeding the single-ended output of the voltage combiner, which is used for combining the differential output of the S-to-D converter, to the input of the LNA through the feedback network, a wideband S-to-D LNA exploiting negative feedback is implemented. By using shunt-peaking of the source follower (SF) based active inductor, the proposed S-to-D LNA can achieve wider loop gain bandwidth with balun functionality. The 3-dB gain bandwidth of the proposed S-to-D LNA is above 5 GHz and the NF is below 4 dB from 100 MHz to 5 GHz. An average voltage gain of 18 dB and an ΠΡ3 of −5 dBm are obtained.