Oguz Tosun

Thread vulnerability in parallel applications

Continuously reducing transistor sizes and aggressive low power operating modes employed by modern architectures tend to increase transient error rates. Concurrently, multicore machines are dominating the architectural spectrum today in various application domains. These two trends require a fresh look at resiliency of multithreaded applications against transient errors from a software perspective. In this paper, we propose and evaluate a new metric called the Thread Vulnerability Factor (TVF). A distinguishing characteristic of TVF is that its calculation for a given thread (which is typically one of the threads of a multithreaded application) does not depend on its code alone, but also on the codes of the threads that share resources and data with that thread. As a result, we decompose TVF of a thread into two complementary parts: local and remote. While the former captures the TVF induced by the code of the target thread, the latter represents the vulnerability impact of the threads that interact with the target thread. We quantify the local and remote TVF values for three architectural components (register file, ALUs, and caches) using a set of ten multithreaded applications from the Parsec and Splash-2 benchmark suites. Our experimental evaluation shows that TVF values tend to increase as the number of cores increases, which means the system becomes more vulnerable as the core count rises. We further discuss how TVF metric can be employed to explore performance-reliability tradeoffs in multicores. Reliability-based analysis of compiler optimizations and redundancy-based fault tolerance are also mentioned as potential usages of our TVF metric.

Fusion of map matching and traffic sign recognition

This paper presents a high performance and robust system for traffic sign recognition with digital map fusion. The proposed system is enhanced by fusion of different sensors and recognition is improved. Traffic sign is detected by a monochrome camera added by a reflective surface detector whereas recognition is achieved by a template matching algorithm. Digital Maps used in this work are standard navigable data. For localization the GPS receiver and the odometer of the test vehicle is used with the developed particle filter based map-matching algorithm. Tests are accomplished in rural and urban areas of metropolitan city for both day and night conditions. Especially, success rate at night scenes is comparably higher when compared to existing approaches and technologies. The system is unique since it is not limited to certain sign types, can be used in day and night conditions. The proposed system can be easily adapted to real world applications since it utilizes low cost and industrially available digital map content and sensors.

Parallelizing Broad Phase Collision Detection Algorithms for Sampling Based Path Planners

Collision checking takes most of the time in sampling based path planning algorithms. When the scene gets crowded, more samples are needed and the probability decreases to find a collision free sample. Broad phase algorithms are designed to eliminate obviously collision free samples, so narrow phase algorithms can concentrate on fewer samples suspected to be in collision. In this study, we compare the performance of two broad phase algorithms implemented on both CPU and GPU. A novel technique is proposed to provide load balancing and efficient cache utilization on Bounding Sphere Collision Detection algorithm. Furthermore, Thrust library is extensively utilized on Sweep and Prune (SAP) algorithm. Our experimental results indicate speedups up to 103 times faster for GPU-based SAP algorithm and 134 times faster for GPU-based Bounding Sphere algorithm, compared to CPU implementations. This may allow using sampling based path planning algorithms for scenes with many robots.

Performance and Energy Efficient Asymmetrically Reliable Caches for Multicore Architectures

Modern architectures are increasingly susceptible to transient and permanent faults due to continuously decreasing transistor sizes and faster operating frequencies. The probability of soft error occurrence is relatively high on cache structures due to the large area of the logic compared to other parts. Applying fault tolerance unselectively for all caches has a significant overhead on performance and energy. In this study, we propose asymmetrically reliable caches aiming to provide required reliability using just enough extra hardware under the performance and energy constraints. In our framework, a chip multiprocessor consists of one reliability-aware core which has ECC protection on its data cache for critical data and a set of less reliable cores with unprotected data caches to map noncritical data. The experimental results for selected applications show that our proposed technique provides 21% better reliability for only 6% more energy consumption compared to traditional caches.

Quantifying Thread Vulnerability for Multicore Architectures

Continuously reducing transistor sizes and aggressive low power operating modes employed by modern architectures tend to increase transient error rates. Concurrently, multicore machines are dominating the architectural spectrum in various application domains. These two trends require a fresh look at resiliency of multithreaded applications against transient errors from a software perspective. In this paper, we propose and evaluate a new metric called the Thread Vulnerability Factor (TVF). A distinguishing characteristic of TVF is that its calculation for a given thread (which is typically one of the threads of a multithreaded application) does not depend on its code alone, but also on the codes of the threads that share data with that thread. As a result, we decompose TVF of a thread into two complementary parts: local and remote. While the former captures the TVF induced by the code of the target thread, the latter represents the vulnerability impact of the threads that interact with the target thread. We quantify the local and remote TVF values for three architectural components (register file, ALUs, and caches) using a set of four multithreaded applications. Our experimental evaluation shows that TVF values tend to increase as the number of cores increases which means the system becomes more vulnerable as the core count rises. We also discuss how TVF values and execution cycles together can be used to explore performance-reliability tradeoffs in multicores at a source code level.

Protecting Code Regions on Asymmetrically Reliable Caches

Cache structures in a multicore system are considerably susceptible to soft errors. Protecting all caches using fault tolerance techniques has notable overheads on performance and power consumption. In this paper, we propose an enhanced protection mechanism for reliability-based critical code regions of the applications on asymmetrically reliable cores which have different error-tolerant cache structures. In this system, software threads which execute reliability-based critical code regions are mapped onto the protected cores, whereas the threads which execute non-critical regions are mapped to the unprotected ones, dynamically during the execution. Our experimental evaluations indicate that the proposed system improves Silent Data Corruption SDC rate by 66i¾ź% with 22i¾ź% performance loss and 1.2i¾ź% more power consumption for selected applications relative to the unprotected caches on average.

Reliability-aware core partitioning in chip multiprocessors

Executing multiple applications concurrently is an important way of utilizing the computational power provided by emerging chip multiprocessor (CMP) architectures. However, this multiprogramming brings a resource management and partitioning problem, for which one can find numerous examples in the literature. Most of the resource partitioning schemes proposed to date focus on performance or energy centric strategies. In contrast, this paper explores reliability-aware core partitioning strategies targeting CMPs. One of our schemes considers both performance and reliability objectives by maximizing a novel combined metric called the vulnerability-delay product (VDP). The vulnerability component in this metric is represented with Thread Vulnerability Factor (TVF), a recently proposed metric for quantifying thread vulnerability for multicores. Execution time of the given application represents the delay component of the VDP metric. As part of our experimental analysis, proposed core partitioning schemes are compared with respect to normalized weighted speedup, normalized weighted reliability loss and normalized weighted vulnerability delay product gain metrics for various workloads of benchmark applications.

Examining Thread Vulnerability analysis using fault-injection

With the scale down of transistor sizes and higher frequencies with low power modes in modern architectures, the chip components become more susceptible to transient errors. Concurrently, multicore machines are replacing traditional single-core machines in most application domains. Thread Vulnerability Factor (TVF) is a metric to evaluate relative soft error vulnerability of multithreaded applications running on multicore architectures. It makes possible vulnerability analysis of parallel programs by providing comparisons between them. In this work, we design a simulation-based fault-injection framework to evaluate soft error vulnerability of parallel applications and perform a validation study to evaluate parallel program vulnerability. The results of the simulation-based fault injection framework is compared with the results based on TVF analysis. Our results demonstrate that TVF provides an efficient vulnerability analysis by having the same ordering and similar vulnerability rates with fault-injection results for a set of multithreaded applications.

Particle simulation on the Cell BE architecture

This paper presents two parallel formulations for the Barnes-Hut algorithm on the Cell architecture, which differ in tree distribution and construction phases of the algorithm. In the initial parallelization, the domains are dynamically partitioned and assigned to the synergistic processing elements (SPEs), and SPEs construct local trees of the sub-domains in parallel. The enhanced parallelization scheme provides better clustering of the particles by sequentially constructing the global tree of the entire work space in the power processing element (PPE) and by partitioning the tree into sub-trees that can fit in the Local Store. SPEs operate on the sub-tree data and construct local trees in parallel. Our experimental evaluation indicates that this application performs much faster on the Cell BE compared to the Intel Xeon based system. Specifically, our first and second methods on the Cell BE outperform Intel Xeon by a factor of 5.8 and 7.1 for 8192 particles, respectively.

A selective protection scheme of applications using asymmetrically reliable caches

A chip multiprocessor framework which contains at least one high reliability core and several number of low reliability cores has been proposed and evaluated. High reliability cores provide ECC protection on their L1 instruction and data caches. Conversely, low reliability cores do not utilize any protection mechanisms.We extract reliability-based critical code regions of the applications by examining function execution time percentages and function call graph, statically.We perform a comparative study to show the efficiency of our framework by using a diverse set of applications from known benchmarks. Cache structures in a multicore system are highly vulnerable to soft errors. Enabling fault tolerance capabilities on all cache structures in a system is inefficient in terms of performance and power consumption. In this study, we propose an enhanced protection mechanism for code segments, which are critical in terms of reliability, by utilizing asymmetrically reliable cores under performance and power constraints. Our proposed system contains at least one high-reliability core, which has an ECC-protected L1 cache, and several low-reliability cores, which have no protection mechanisms. Reliability-based critical code regions are assumed to be high-priority functions, which are extracted by examining the execution time percentages and the programs call graph in our framework, statically. Software threads that invoke one of the high-priority functions are bound to the high-reliability cores dynamically during the execution, while the threads that execute the remaining functions are bound to the low-reliability cores. As part of the experimental analysis, our proposed framework is compared with traditional fully protected and unprotected configurations with respect to performance, power and reliability metrics for various applications of the benchmarks. Our framework exploits the benefits of providing the reliability-based critical regions of the applications exclusively by offering notable power and cost savings with close performance and reliability values for the set of functions reported in the experimental results.