Oi-Ying Wong

Dynamic Analysis of Two-Phase Switched-Capacitor DC–DC Converters

A method that aims at analyzing the dynamic behavior of some two-phase switched-capacitor charge pump circuits is proposed. A recurrence relation on the voltages across the charging capacitors of a given two-phase charge pump circuit is developed. The output voltage and the accumulated charge of a charge pump circuit after any clock cycle were found by solving some basic matrix equations, with a specific loading current and some required initial conditions. The validation of the proposed method was done by SPICE simulations based on a 8 × linear, Fibonacci, and an exponential charge pump. The analysis results were also verified with the simulation results obtained from some charge pump circuits designed with the 0.18 μm CMOS process. Results show that the proposed method can yield a close estimation on the dynamic behavior of a charge pump circuit in most of the designs. We further found that the rising times for the exponential and Fibonacci charge pumps are shorter, especially when the conversion ratio is high, than that of the linear one.

An overview of charge pumping circuits for flash memory applications

Charge pump is an indispensable component in flash memory systems in order to generate high operation voltages for programming flash memory cells. In this paper, we review some high-efficiency charge pump circuits that fulfill the stringent requirements in modern flash memory technology. The performance of these charge pump circuits will be compared in terms of voltage conversion efficiency, power efficiency, area, and process requirement. Some advanced charge pump circuits proposed recently will also be introduced.

High-Performance Resistorless Sub-1V Bandgap Reference Circuit Based on Piecewise Compensation Technique

A piecewise compensated sub-lV CMOS bandgap reference without using any resistors is presented. The design reduces the silicon chip area with improved circuit robustness. The bandgap reference is simulated with Spectre using SMIC 0.18 mum CMOS technology. It operates at a minimum voltage of 1.5 V and generates a stable voltage at 0.658 V with minimal temperature coefficient of plusmn 5.36 ppm/degC for temperature ranging from -10 to 130degC. It has a line regulation of 0.89% and a high power supply rejection ratio of -42.3 dB. The power consumption of this circuit is as low as 0.229 mA at 1.5 V input voltage.

Design strategy for two-phase switched capacitor step-up charge pump

This paper presents a systematic approach to generate 2-phase switched capacitor DC-DC step-up converters with a given integer conversion ratio. The present method has a deterministic complexity and does not require any search. The generated charge pumps make use of theoretical minimum number of capacitors to achieve conversion ratios from 2 to 29, and almost theoretical minimum number of capacitors for all other conversion ratios. Design examples are presented to illustrate the proposed method.

A dynamic-biasing 4× charge pump based on exponential topology

A 4× charge pump using exponential topology is proposed and implemented. Comparing to the conventional implementations, the proposed circuit suppresses the reverse current effectively without using different threshold-voltage transistors and additional capacitors. Also, the body effect found in the charge transfer switches is eliminated. The proposed charge pump is analyzed with the state-space method and fabricated using 0.35µm complementary metal-oxide-semiconductor process. Results show that the output voltages close to the ideal one, and a maximum power efficiency of 95% was recorded. Copyright

A low-voltage charge pump with wide current driving capability

A high current driving capability charge pump circuit is proposed. By adopting the dynamic boosting circuit, the overdrive voltages of all the charge transfer switches (CTSs) in the charge pump are maintained for a large loading current. In addition, the largest voltage difference between any of the terminals of all the transistors does not exceed the supply voltage VDD, and solves the gate-oxide overstress problem in the conventional charge pump circuits and enhances the reliability. Other advantages of the proposed charge pump include high pumping efficiency because of no threshold voltage drop and 2-phase operation, without the need of extra power consumption on the logic circuits and drivers. The proposed charge pump circuit is designed and simulated based on a low voltage process. Results show that the charge pump can operate in a wide output current range.

A novel gate boosting circuit for 2-phase high voltage CMOS charge pump

A novel gate boosting circuit is proposed for general switched-capacitor charge pump. The proposed circuit only requires two small transistors to generate the necessary driving signal from a clock signal that swings between 0V to VDD for closing and opening the charge transfer switches in the charge pump. As a result, the proposed gate boosting circuit reduces the design complexity and silicon area. Moreover, the regular structure eases the layout and increases the reliability of the implemented charge pump. A 3× Makowski charge pump implemented by the proposed gate boosting element is simulated. An output voltage closed to the ideal one shows that the proposed gate boosting circuit is suitable to be used in designing high efficiency charge pumps.

AN ENERGY EFFICIENT HALF-STATIC CLOCK-GATING D-TYPE FLIP-FLOP

This paper presents a new design of half-static clock-gating D flip-flop (DFF). The proposed DFF consists of a dynamic master and a half-static slave built with a pass-transistor clock- gating circuitry. The new circuit greatly reduces the total power dissipation, especially in the low data activity cases, and saves a lot of silicon area. The performance of the proposed DFF is verified with SPICE simulation using the 0.18 mum mixed-signal CMOS technology. The overall performance of the present design is much better than numerous DFFs reported in the literatures.

Analysis of ESD discharge current distribution and area optimization of VDMOS gate protection structure

Abstract The VDMOS Electrostatic Discharge (ESD) protection structure using back-to-back connected zener diode on poly-Si film has been studied. The study reveals that there exists an effective range for the values of the current distribution resistors and optimal size of the zener diode to maximize the ESD protection. A model is proposed to analyze the effect of the current distribution resistors and the size of the zener diode. We also propose a design rule for optimizing the size of the ESD protection structure under the constraint of ESD voltage. The presented analytical model is validated with experimental measurements.

Area efficient 2 n × switched capacitor charge pump

An area efficient switched capacitor charge pump based 2n× voltage converter constructed by cascading n units of identical cells with cross-coupled charge pump is proposed and is implemented with a boosting dynamic circuit to provide level shifting. The proposed charge pump can be implemented using standard high-voltage CMOS process. Simulation result of a 4× charge pump based on 0.35µm CMOS technology is presented to demonstrate the effectiveness of the proposed circuit.