Olena Hebda

Design of Moore finite state machine with coding space stretching

The proposed method is targeted on reduction of hardware amount in logic circuit of Moore finite-state machine implemented with programmable logic arrays (PLA). The method is based on using more than minimal amount of variables in codes of FSM internal states. The method includes two stages of state encoding. The second stage is connected with recoding of states inside each class of pseudoequivalent states.

Design of Moore finite state machine with extended coding space

The proposed method is targeted on reduction of hardware amount in logic circuit of Moore finite-state machine implemented with programmable logic arrays (PLA). The method is based on using more than minimal amount of variables in codes of FSM internal states. The method includes two stages of state encoding. The second stage is connected with recoding of states inside each class of pseudoequivalent states.

Synthesis of PLA-Based Moore FSM with Unconventional Presentation of State Codes

Abstract The method is proposed for reduction of hardware amount in logic circuit of Moore finite state machine implemented with PLAs. It is based on using classes of pseudoequivalent states. Each a class corresponds to a unique state of equivalent Mealy FSM. In this method the next state code is represented as a concatenation of codes for class of pseudoequivalent states and collection of output variables. Such an approach allows the elimination of dependence among states and output variables.

Design of moore finite state machine with extended state codes

The new method is proposed for reduction of chip area occupied by logic circuit of Moore FSM implemented with PLAs. It is based on the representation of the state code as a concatenation of the code of class of pseudoequivalent states and code of state inside this class. Such an approach allows elimination of dependence among states and output variables. It allows the hardware reduction in the FSM logic circuit in comparison with known design methods.

Matrix implementation of Moore FSM with nonstandard presentation of state codes

The method is proposed for reduction of hardware amount in logic circuit of Moore finite state machine. The method is oriented on customized matrix technology. It is based on representation of the next state code as a concatenation of codes for class of pseudoequivalent states and collection of microoperations. Such an approach allows elimination of dependence among states and microoperations. As a result, both circuits for generation of input memory functions and microoperations are optimized. An example of the proposed method application is given.

Hardware reduction for matrix circuit of control Moore automaton

The method is proposed for reduction of the area of matrix implementation of the circuit of the Moore finite state machine (FSM). The method is based on optimal state coding and decomposition of a matrix of terms on two sub-matrixes. Thus classes of the pseudoequivalent states are used. Such approach allows to reduce number of lines of the table of transitions of Moore FSM up to this value of the equivalent Mealy FSM. As a result the area of the matrixes forming excitation function of a states memory register is optimized. An example of the proposed method application is given.