Oliver Aubel

Grain structure analysis and effect on electromigration reliability in nanoscale Cu interconnects

The grain structure in Cu interconnects of the 45 nm node was analyzed to yield grain orientation and boundary characteristics using a high-resolution electron diffraction technique. A dominant sidewall growth of {111} grains was observed, reflecting the importance of interfacial energy in controlling grain growth below 70 nm linewidth. The grain structure was used to identify flux divergent sites for void formation under electromigration (EM) and to analyze the effect on EM statistics for Cu lines with CoWP capping using a microstructure-based model. This analysis established a correlation between the microstructure of Cu nanolines, void formation kinetics, and EM statistics.

Electromigration early failure void nucleation and growth phenomena in Cu and Cu(Mn) interconnects

Electromigration early failure void nucleation and growth phenomena were studied using large-scale, statistical analysis methods. A total of about 496,000 interconnects were tested over a wide current density and temperature range (j = 3.4 to 41.2 mA/μm2, T = 200 to 350°C) to analyze the detailed behavior of the current density exponent n and the activation energy Ea. The results for the critical V1M1 downstream interface indicate a reduction from n = 1.55±0.10 to n = 1.15±0.15 when lowering the temperature towards 200°C for Cu-based interconnects. This suggests that the electromigration downstream early failure mechanism is shifting from a mix of nucleation-controlled (n = 2) and growth-controlled (n = 1) to a fully growth-controlled mode, assisted by the increased thermal stress at lower temperatures (especially at use conditions). For Cu(Mn)-based interconnects, a drop from n = 2.00±0.07 to n = 1.64±0.2 was found, indicating additional effects of a superimposed incubation time. Furthermore, at lower current densities, the Ea value seems to drop for both Cu and Cu(Mn) interconnects by a slight, but significant amount of 0.1 - 0.2eV. Implications for extrapolations of accelerated test data to use conditions are discussed. Furthermore, the scaling behavior of the early failure population at the NSD=-3 level (F~0.1%) was analyzed, spanning 90, 65, 45, 40 and 28 nm technology nodes.

Stress-induced phenomena in nanosized copper interconnect structures studied by x-ray and electron microscopy

We present the first dynamic study of damage mechanisms in nanosized on-chip Cu interconnects caused by stress-induced voiding in advanced integrated circuits. Synchrotron-based transmission x-ray microscopy is applied to visualize the void evolution and conical dark-field analysis in the transmission electron microscopy to characterize the Cu microstructure. Our x-ray microscopy measurements showed, in contradiction to electromigration studies, no void movement over large dimensions during the stress-induced void evolution. We observed in via/line Cu interconnect structures that voids are formed directly beneath the via, i.e., in the Cu wide line at the edge of the via bottom. It is concluded that voids are originally formed at the site where eventually the catastrophic failure occurs. During stress migration tests, Cu atoms migrate from regions of low stress to regions of high tensile stress, and simultaneously, vacancies migrate along the stress gradient (within a limited range of some microns) in the ...

Stress migration model for Cu interconnect reliability analysis

Stress migration (SM) reliability data have been treated qualitatively to define pass or fail criteria in the past. However, realistic quantitative SM analysis and lifetime estimates for products were not available due to lack of a suitable SM model. In this paper, we establish a comprehensive SM model for quantitative stress-induced-voiding (SIV) risk analysis for 32 nm technology and beyond. It was found that the SIV risk is dependent on both stress temperatures and geometric structural line widths as driving forces. Based on the new SM model, the SM lifetime can be estimated from measurable SM data and accelerated SM test methods can be designed to meet the qualification criteria.

Effects of cap layer and grain structure on electromigration reliability of Cu/low-k interconnects for 45 nm technology node

The effects of cap layer and grain structure on electromigration (EM) reliability of Cu/low-k interconnects were investigated for the 45 nm technology node. Compared to the SiCN cap only, the CoWP capped samples showed a 40x lifetime improvement with a small lifetime variation (σ=0.34) at the M1 level. By tuning the process parameter, Cu lines of two different grain sizes were fabricated at the M2 level for both with and without the CoWP cap. The EM results showed that, for both caps, the Cu lines with the large grain structure had a longer EM lifetime compared with the small grain structure, and the EM enhancement of the metal cap was reduced for the small grain structure. Failure analysis revealed two failure modes for the SiCN cap, with void formation either at the via corner or in the trench away from the via; on the contrary, voids mostly formed several microns away from the via for the large grain CoWP cap. The difference in voiding locations for the two caps was attributed to the different interfacial mass transport rate. Implications of scaling effect on EM reliability were also discussed.

Investigation of stress distribution in via bottom of Cu-via structures with different via form by means of submodeling.

Abstract In ULSI multilevel metallizations the via bottom is the main region for the appearance of local stress. This local stress can lead to fractures or porous spots. Out of this concerning the local stress distribution the via bottom region has to be investigated. Due to various technological processes the via shape especially the via bottom geometries are different. In this paper FE-Simulations with respect to the different via bottom geometries and different temperatures of the process steps will be presented. The best via bottom geometry is figured out. The submodeling technique in ANSYS ® is used for these investigations for reduction of simulation time and precise results. The thickness of the barrier has also an influence on the mechanical stress and will be also investigated.

In situ study on low-k interconnect time-dependent-dielectric-breakdown mechanisms

An in situ transmission-electron-microscopy methodology is developed to observe time-dependent dielectric breakdown (TDDB) in an advanced Cu/ultra-low-k interconnect stack. A test structure, namely a “tip-to-tip” structure, was designed to localize the TDDB degradation in small dielectrics regions. A constant voltage is applied at 25 °C to the “tip-to-tip” structure, while structural changes are observed at nanoscale. Cu nanoparticle formation, agglomeration, and migration processes are observed after dielectric breakdown. The Cu nanoparticles are positively charged, since they move in opposite direction to the electron flow. Measurements of ionic current, using the Triangular-Voltage-Stress method, suggest that Cu migration is not possible before dielectric breakdown, unless the Cu/ultra-low-k interconnect stacks are heated to 200 °C and above.

A simple electrical method for etch bias and process reliability determination

A fast and simple electrical method is developed to characterize the etch bias and post-patterned ILD breakdown strength of back-end-of-line (BEOL) interconnects, as well as the middle-of-line (MOL) contact/poly module. The method provides a timely and valuable monitoring mechanism for assessing lithography, etch, thin-film quality and process reliability windows.

EM and SM induced degradation dynamics in copper interconnects studied using electron microscopy and X-ray microscopy

In addition to statistically relevant standard reliability tests and lifetime analysis, the study of solid-state physical degradation mechanisms for a limited number of representative samples is needed to understand weaknesses in the interconnect technology and to exclude reliability-related failure in Cu interconnects. We present dynamic studies of damage mechanisms in on-chip Cu interconnects caused by electromigration (EM) and stress migration (SM). Scanning electron microscopy (SEM) and synchrotron-based transmission X-ray microscopy (TXM) are applied to visualize the void evolution, electron backscatter diffraction (EBSD) in the SEM and conical dark-field (CDF) analysis in the transmission electron microscope (TEM) are applied to characterize the Cu microstructure. In case of EM, our experiments show that voids are formed at interfaces and grain boundaries, often far away from vias in via/line interconnect structures. Due to the gradient of the electrical potential, Cu atoms migrate along weak pathways for material transport. Depending on the interface strength, voids that virtually move along interfaces or grain boundaries over large distances into the opposite direction of the current flow, i. e. toward the cathode end of the line, have been visualized. In case of SM, our experiments do not show void movement over large distances during the stress-induced voiding (SIV). In via/line interconnect structures we rather observe that voids are formed directly beneath the via, i. e. in wide Cu line at the edge of the via bottom. It is concluded that voids are originally formed at the site where eventually the catastrophic failure occurs. During SM tests, Cu atoms migrate from regions of low tensile (or high compressive) stress to regions of high tensile stress, and simultaneously, vacancies migrate along the stress gradient (within a limited range of some μm) in the opposite direction, to the location where vias connect wide Cu lines. For both EM and SM, the driving forces for atomic transport depend strongly on the particular geometry of the tested structure, but also on interface bonding and metal microstructure.

Advanced metallization concepts and impact on reliability

This study examines several possible back-end-of-line process options for future leading edge, high performance semiconductor devices, discussing effects on electrical and reliability characteristics as well as specific processing challenges. The extendibility of current physical vapor deposition-based processes for barrier layers, based on existing tool sets and therefore representing the most cost-efficient solution, is reviewed. Subsequently, alloying options such as Cu(Mn) in the seed are highlighted, showing excellent reliability, but also leading to challenges with electrical performance. Furthermore, the applicability of atomic layer and chemical vapor deposition processes for barrier applications and their limits are examined. The electromigration advantage of selective metallic capping processes such as electroless cobalt–tungsten–phosphorus deposition and chemically-vapor-deposited cobalt is highlighted, while process challenges are shown. Additionally, the need for careful adjustment of the Cu plating process and evaluation of electromigration performance upon changes to the barrier/liner/seed process is discussed.