Oliver D. Patterson

In-line E-beam metrology and defect inspection: industry reflections, hybrid E-beam opportunities, recommendations and predictions

At SPIE 2013 in Metrology, Inspection, and Process Control for Microlithography an invited paper was published titled “In-line E-beam wafer metrology and defect inspection: the end of an era for image-based critical dimensional metrology? New life for defect inspection”. Three years have passed and numerous developments have occurred as predicted in this paper. The development of E-beam tools that can concurrently handle metrology and defect applications is one of the primary developments. In this paper, the capabilities of these new E-beam tools and their current use cases will be discussed in the areas of Critical Dimension Uniformity (CDU), In-die overlay, Hot spot and Physical defect inspection. Emphasis will be placed on use cases where “massive” CDU data is collected in order to increase yield learning for manufacturing (14nm) and decrease cycles of learning for development (7nm). Additionally, some of the other subject material from the previous publication will also be discussed such as the current state of E-beam critical dimension image fidelity and physical defect detection capabilities. Lastly, future directions and opportunities for In-line E-beam including Multi-beam and/or Multi-column E-beam will be discussed.

In-line characterization of EDRAM for a FINFET technology using VC inspection

An E-beam voltage contrast inspection methodology involving multiple inspection points has been created to support development of the EDRAM module for a recent FINFET technology. This methodology provides within-sector feedback for a wide range of defect types enabling fast turn-around of split experiments and early detection of process excursions. Most defectivity affecting EDRAM is buried and therefore not detectable with broad beam plasma inspection. The EDRAM module is first in the process sequence for this FINFET technology. Without E-beam inspection, the first opportunity for defectivity feedback would be metal 1 test, which is months later in the process sequence. While direct E-beam inspection of functional EDRAM is a key part of this methodology, many defect types cannot be detected directly on functional SRAM. Special voltage contrast test structures were designed to monitor these defect types. The key defect types and the strategy used to detect each of them is described in detail in this paper. Select split experiment and process excursion data are used to illustrate the impact of the methodology.

The Benefits of High Landing Energy for E-Beam Inspection

E-beam inspection has become one of the most important tools for rapid yield ramp in the semiconductor industry, due to its ability to detect a wide range of defects in-line soon after their formation. This role expansion is due to the increasing difficulty in detecting defects in-line with other traditional methods as well as the continuing evolution of e-beam capability. In the last five years, the role of e-beam inspection has expanded from detection of electrically active, buried defects using voltage contrast inspection to also detection of many challenging physical defect types as well as systematic patterning defects. This paper reports on the impact of an important recent improvement in e-beam inspection tool capability, the availability of dramatically higher landing energies, and the benefits this improvement provides. These include detection of buried defects, a sharper image for detection of surface physical defects, minimization of wafer charge enabling much longer inspections, and material contrast. These advantages are illustrated through a number of examples. High landing energy can damage certain wafer surfaces and these concerns are also discussed. Overall, high landing energy is a powerful new tool in the e-beam inspection tool box which should be aggressively adopted.

E-Beam mechanics and net connectivity for interlayer short detection

The concept of layout-centric defect inspection targeting specific configurations of design is not new. The majority of design-based Micro Care Areas (MCA) relies on historical findings - translating failing topologies from Failure Analysis (FA), Design-for-Manufacturing (DFM), and other sources into targeted zones tailored for inspection. However, there exists an inherent flaw to this model tied to physical limitations of top-down optical inspection. There exists a subset of physical defects that are invisible to optical inspection tools, in particular interlayer defects that interact with prior level masks. For such applications, defect engineering will turn to Electron-Beam (E-beam) Voltage Contrast Inspection (VCI) - which compares the response of a wafer feature subjected to electron charging, measured in grey level differences, of a candidate defect to a reference. In our previous paper “Net Tracing and Classification Analysis on E-Beam Die-to-Database” [3], we illustrated the merits of factoring feature connectivity as a means of differentiating between real voltage-contrast defects, specifically that of dark voltage-contrast (DVC), and nuisance. Our novel methodology takes into consideration the inspectability of a targeted feature before generating components for design-based inspection. The process has the obvious consequence of decreasing the total area of inspection and subsequent benefit of reducing the inspection time. The concept is intuitive - a wafer feature, typically a Via, with a dark optical response when a bright response is expected is indicative of either blockage in the connected electrical net or otherwise disconnect between features. That said, DVC is but a subset of detectable defects with E-beam. This paper reports a novel approach in capturing defects of the other subset of the population, bright voltage-contrast (BVC) and its implications, through exercising the same principle of inspectability.

Solved: The mystery of bright voltage contrast word-line defects for SOI technology using Nanoprobing

Early development of new semiconductor technologies heavily centers around the use of SRAM. For SOI technologies, voltage contrast (VC) inspection is commonly used to detect contact opens but the signal commonly associated with shorting, bright VC, has traditionally been ignored because too many failure analysis results have resulted in “no defect found”. For a recent SOI, Replacement Metal Gate (RMG), FINFET technology, word-line (WL) bright defects again were routinely detected. Through a variety of characterization techniques including straight-forward inspection followed by failure analysis (FA) validation, comparison of results between inspection levels including the use of virtual drive-backs, Nanoprobing, and the use of VC test structures, a better understanding of these WL bright defects for SOI technology was developed. Discussion of the inspection work at the RMG level includes an explanation of interesting charging dynamics. WL bright defects can be due to actual TS to gate pattern (PC) shorts, but also slight source/drain leakages when VG is below VT or gate dielectric shorts. These latter causes are impossible to see via straight-forward FA. Through the use of Nanoprobing, this mystery has finally been solved.

Full-Wafer Voltage Contrast Inspection for Detection of BEOL Defects

This paper details an application where E-beam inspection (EBI) can be used for 100% full wafer inspection, generally considered a mythical target for EBI. For process layers where the line-widths and defects of interest are large, very large pixel size and high scan frequency can be used, thereby making full wafer inspection feasible. The metal layers in the back-end-of-line fit this bill when scanned in voltage contrast (VC) mode. Shorts or opens at any previous layer connected to the surface nodes can cause a VC signal, therefore the electrical health of each wafer is assessed for multiple layers simultaneously across the full wafer. The advantage of this scan is that failure sites can be identified and somewhat localized well before wafer final test. This application is more appropriate for semi-mature technologies where there are few defects per wafer, and therefore a full wafer scan is needed to catch a reasonable number of defects. The challenge with this type inspection is in identification of the root cause. A number of studies to map VC defect strength to types of physical defects are described. These studies demonstrated that this technique successfully finds yield limiting defects, but not all yield limiting defects will be detected. A plan for how to use the VC inspection to find root cause is presented.