Olivier Bonnin

Low leakage and low variability Ultra-Thin Body and Buried Oxide (UT2B) SOI technology for 20nm low power CMOS and beyond

We fabricated CMOS devices on Ultra-Thin Boby and Buried Oxide SOI wafers using a single mid-gap gate stack. Excellent global, local and intrinsic V<inf>T</inf>-variability performances are obtained (A<inf>VT</inf>=1.45mV.µm). This leads to 6T-SRAM cells with good characteristics down to V<inf>DD</inf>=0.5V supply voltage and with excellent Static Noise Margin (SNM) dispersion across the wafer (σ<inf>SNM</inf><SNM/6) down to V<inf>DD</inf>=0.7V. We also demonstrate ultra-low leakage (<0.5pA/µm) on UT2B devices at L<inf>G</inf>= 30nm by source/back biasing thanks to a low gate current and Gate Induced Drain Lowering (GIDL).

Fabrication of

Segmented-channel Si₁_-_xGe_x/Si p-channel MOSFETs are fabricated using a conventional process, starting with corrugated Si₁_-_xGe_x/Sisubstrates. As compared with the control devices fabricated using the same process but starting with a noncorrugated Si₁_-_xGe_x/Si substrate, the segmented-channel MOSFETs show better layout efficiency (30% higher <i>I</i>_ON for <i>I</i>_OFF = 10 nA per micrometer layout width) due to enhanced hole mobility and dramatically reduced dependence of performance on layout width due to the geometrical regularity of the channel region.

\hbox{Si}_{1 - x}\hbox{Ge}_{x}/\hbox{Si}

Smart Cut™ technology is used to manufacture Strained-SOI (sSOI) substrates. These substrates are proposed to boost performance for both planar and FinFET Fully Depleted SOI devices. To comply with tight transistor variability requirements, strong emphasis has been put on layer thickness control and low stress variation. A 1.2 Å RMS roughness and less than 10% stress fluctuation are already demonstrated for sSOI wafers.

pMOSFETs Using Corrugated Substrates for Improved

Thickness uniformity of the Ultra Thin SOI (UTSOI) substrates is one of the key criteria to control Vt variation of the planar FDSOI devices. We present an evolutionary approach to SmartCutTM technology which already allows achieving a maximum total SOI layer thickness variation of less than ± 10 Å on preproduction volume. Total thickness variation of ± 5 Å is targeted.

I_{\rm ON}

Segmented-channel Si_1-xGe_x/Si pMOSFETs are fabricated using a conventional process, starting with a corrugated Si_1-xGe_x/Si substrate. As compared with control devices fabricated using the same process but starting with a non-corrugated Si_1-xGe_x/Si substrate, the segmented-channel MOSFETs show better layout efficiency (30% higher I_ON for I_OFF=10 nA per μm layout width) due to enhanced hole mobility, and dramatically reduced dependence of performance on layout width due to the geometrical regularity of the channel region.

and Reduced Layout-Width Dependence

Recent UTBB device data at sub-25nm gate length demonstrate good performance, small VT variation and excellent low power operation. In addition, very uniform Soitec Xtreme SOI™ product substrates are now available and compliant with device requirements. Thus the level of maturity of UTBB devices and substrates makes it possible for introduction at 20nm node. Multiple options at the substrate level to further boost the performance open up the path to improve performance for future nodes.

Strained silicon on insulator substrates for fully depleted application

Now that silicon product results are becoming available, and that the FD-SOI substrates hit the required uniformity to enable such products. It can now be said that Planar FDSOI is a credible manufacturing technology at 28nm. Furthermore, the technology is in place and has been proven to enable further scaling to at least the 10nm node.