Byron Ho

Effectiveness of Stressors in Aggressively Scaled FinFETs

The stress transfer efficiency (STE) and impact of process-induced stress on carrier mobility enhancement in aggressively scaled FinFETs are studied for different stressor technologies, substrate types, and gate-stack formation processes. TCAD simulations show that strained-source/drain STE is 1.5× larger for bulk FinFETs than for SOI FinFETs. Although a gate-last process substantially enhances longitudinal stress within the channel region, it provides very little improvement in electron mobility over that achieved with a gate-first process. Guidelines for FinFET stressor technology optimization are provided, and performance enhancement trends for future technology nodes are projected.

Design Optimization of Multigate Bulk MOSFETs

The design optimization of multigate bulk MOSFET structures is investigated for sub-20-nm gate lengths. Three-dimensional device simulations were used to optimize device design parameters such as the retrograde channel doping profile, as well as the length, width, and height of the gated channel region. Compared with the FinFET design, the results indicate that the tri-gate MOSFET design is promising for continued bulk-Si CMOS transistor scaling, because it can achieve similar on-state current performance and intrinsic delay [for the same channel stripe pitch (SP)] at a lower height/width aspect ratio (0.8 versus 2.17) and less aggressive retrograde channel doping gradient for improved manufacturability. Only by increasing the height of the channel region and/or reducing the channel SP can the FinFET bulk MOSFET design achieve better delay, but at the cost of reduced manufacturability.

Carrier-Mobility Enhancement via Strain Engineering in Future Thin-Body MOSFETs

The impact of body-thickness scaling on strain-induced carrier-mobility enhancement in thin-body CMOSFETs with high-k/metal gate stacks, based on quantum-mechanical simulations calibrated with measured data, is presented to provide insight into device performance enhancement trends for future technology nodes.

Impact of back biasing on carrier transport in ultra-thin-body and BOX (UTBB) Fully Depleted SOI MOSFETs

A comprehensive study of the impact of back biasing on carrier transport behavior in Ultra-Thin Body and BOX (UTBB) Fully Depleted SOI (FD-SOI) MOSFETs and its implications for deeply scaled device performance is presented.

Planar GeOI TFET Performance Improvement With Back Biasing

Reverse back biasing of a planar germanium-on-insulator tunneling field-effect transistor provides for significant improvement in <i>I</i>_ON/<i>I</i>_OFF, by over an order of magnitude for 0.25 V operating voltage. Optimization of the gate-to-source overlap and source doping gradient is key to maximizing the benefit of back biasing.

Fabrication of

Segmented-channel Si₁_-_xGe_x/Si p-channel MOSFETs are fabricated using a conventional process, starting with corrugated Si₁_-_xGe_x/Sisubstrates. As compared with the control devices fabricated using the same process but starting with a noncorrugated Si₁_-_xGe_x/Si substrate, the segmented-channel MOSFETs show better layout efficiency (30% higher <i>I</i>_ON for <i>I</i>_OFF = 10 nA per micrometer layout width) due to enhanced hole mobility and dramatically reduced dependence of performance on layout width due to the geometrical regularity of the channel region.

\hbox{Si}_{1 - x}\hbox{Ge}_{x}/\hbox{Si}

Drift-diffusion models are used in conjunction with Monte Carlo simulations to study and compare the scalability of germanium (Ge) versus silicon (Si) p-channel double-gate MOSFETs near the end of the technology roadmap. Direct source-to-drain tunneling (DSDT) and uniaxial compressive stress effects are taken into account. The higher dielectric constant of Ge results in degraded short-channel effects and lower drive currents for a given off-state leakage specification. With large compressive uniaxial channel stress (1.5 GPa), Ge can outperform Si for gate lengths (Lg) greater than 15 nm. Due to its lower effective hole transport mass, Ge suffers more from DSDT, resulting in degraded p-channel MOSFET performance at very short Lg.

pMOSFETs Using Corrugated Substrates for Improved

The inversion-layer hole mobility in MOSFETs with thin silicon-germanium (Si_1-xGe_x) channels grown pseudomorphically on Si is calculated using a self-consistent 6 × 6 <i>k</i> ·<i>p</i> Poisson-Schrödinger mobility simulator calibrated to experimental and simulation data. The addition of uniaxial compressive stress to the inherent biaxial compressive strain of the pseudomorphic Si_1-xGe_x layer is found to further enhance hole mobility by up to 2.5×. Two-dimensional device simulations are used to assess the benefit of the Si_1-xGe_x heterostructure channel for boosting the ON-state current (<i>I</i>_on) of p-channel MOSFETs with a gate length (<i>L</i>_g) of 18 nm; the results show a moderate (10%-40%) improvement over a bulk-Si MOSFET.

I_{\rm ON}

The capability to accurately characterize lateral etch rate is needed for the manufacture of micro/nano-electro-mechanical devices which incorporate air-gaps. Optical microscopy can be used to monitor the etch-front and to detect whether a structure has been completely undercut (“released”), but not if the gap thickness is too small, e.g., less than 10 nm. In this paper, an electrical method of lateral-etch end-point detection is presented. By electrically testing cantilever beams of differing widths, the lateral etch rate can be determined. The accuracy of this method is verified via correlation with optical interferometry (R = 0.998) for gap thicknesses down to 70 nm. This new electrical characterization method is shown to be applicable to gap thicknesses as small as 4 nm.

and Reduced Layout-Width Dependence

Segmented-channel Si_1-xGe_x/Si pMOSFETs are fabricated using a conventional process, starting with a corrugated Si_1-xGe_x/Si substrate. As compared with control devices fabricated using the same process but starting with a non-corrugated Si_1-xGe_x/Si substrate, the segmented-channel MOSFETs show better layout efficiency (30% higher I_ON for I_OFF=10 nA per μm layout width) due to enhanced hole mobility, and dramatically reduced dependence of performance on layout width due to the geometrical regularity of the channel region.