Olivier Gay-Bellile

A reconfigurable superimposed 2D-mesh array for channel equalization

In this paper we present a scalable and reconfigurable mesh array of programmable processing elements. It has been designed to implement multi-standard channel estimation and equalization algorithms for digital television broadcast applications. It particularly introduces the concept of a superimposed array to speed-up the execution of an adaptive filter. This paper also discusses the array configuration and programming tools. The flexibility of this solution is demonstrated, as it simultaneously addresses the mono carrier adaptive equalizer for cable transmission, as well as multicarrier channel estimation and correction for terrestrial transmission. Gate-level synthesis results have shown that this flexibility is obtained at acceptable cost.

Architecture of a programmable FIR filter co-processor

This paper presents a new generic architecture to build co-processors dedicated for FIR filtering algorithms, which can implement a set of different filter like symmetric and adaptive filters with or without decimation. Moreover, it manages various types of data (real or complex) and different data accuracies (8 or 16 bits) owing to a specific operative bloc architecture. For instance, a 60.000 equivalent gates co-processor is described that copes with a 512-tap symmetric filter in 8-bit accuracy with a working frequency of 100 MHz (the computation power is 4.8 Gops). So, it could be used as a powerful co-processor for new generation DSPs such as Philips TriMedia and Texas Instruments TMS320C6201 whenever filtering functions are required as in digital communications.

Array processing for channel equalization

An array of primitive programmable processors has been designed for high throughput reconfigurable signal processing. Each processor retains a primitive instruction set, minimal local storage, and exchanges data with adjacent processors using nearest neighbor communication. Several applications, including an adaptive filter with coefficient update using the least mean squares (LMS) algorithm, have been implemented and evaluated on an array of such processors. A multilayer processor mesh structure is used to accelerate summation of filter products. This paper describes the processor design, array interconnection, programming, and system integration issues, and concludes with the description of a functional LMS adaptive filter.