Geoffrey Francis Burns

Design and implementation of a 16 by 16 low-power two's complement multiplier

This paper describes the design and implementation of a high-speed low-power 16 by 16 twos complement parallel multiplier. The multiplier uses optimized radix-4 Booth encoders to generate the partial products, and an array of strategically placed (3,2), (5,3), and (7,4) counters to reduce the partial products to sum and carry vectors. The more significant bits of the product are computed from left to right using a modified Ercegovac-Lang converter. An implementation of the multiplier in 0.25- /spl mu/m static CMOS technology has an area of 0.126 mm/sup 2/, a measured delay of 4.39 ns, and a average power dissipation of 0.110 mW/MHz at 2.5 Volts and 100/spl deg/C.

VLSI implementation of a 200-MHz 16/spl times/16 left-to-right carry-free multiplier in 0.35 /spl mu/m CMOS technology for next-generation DSPs

We describe the VLSI implementation of a 16/spl times/16 left-to-right carry-free multiplier. Left-to-right multipliers are significantly faster than conventional right-to-left multipliers because they do not require a carry-propagate adder to complete the multiplication process. The key to the high speed of left-to-right multiplication is the fact that the most significant partial product digits are available in carry-save form earlier than they are in conventional right-to-left multipliers. Two conversion schemes for converting the most significant half of the partial products from carry-save to binary form are described. The first scheme uses a variation of the Ercegovac-Lang converter, and the second scheme uses a conventional carry-select adder. Experimental measurements are presented to show the feasibility of 200-MHz operation.

A reconfigurable superimposed 2D-mesh array for channel equalization

In this paper we present a scalable and reconfigurable mesh array of programmable processing elements. It has been designed to implement multi-standard channel estimation and equalization algorithms for digital television broadcast applications. It particularly introduces the concept of a superimposed array to speed-up the execution of an adaptive filter. This paper also discusses the array configuration and programming tools. The flexibility of this solution is demonstrated, as it simultaneously addresses the mono carrier adaptive equalizer for cable transmission, as well as multicarrier channel estimation and correction for terrestrial transmission. Gate-level synthesis results have shown that this flexibility is obtained at acceptable cost.