Olivier Joubert

Process optimization of a negative-tone CVD photoresist for 193-nm lithography applications

New photoresists and processes are required for sub 0.15 micrometers design rules and currently an important effort is on- going for single layer resists optimization at 193 nm. Top surface imaging can be an interesting alternative approach. An all dry chemical vapor deposition (CVD) process based on plasma polymerized methylsilane (PPMS) or plasma polymerized dimethylsilane (PP2MS) provides a thin conformal and photosensitive layer at 193 nm. A thin amorphous film of Si- Si bonded material is deposited using plasma enhanced chemical vapor deposition with methylsilane or dimethylsilane as the gas precursor. Upon 193 nm exposure under air, photo-induced oxidation of the CVD resist occurs, generating a latent image. The image is then developed in a chlorine-based plasma, providing a negative tone process. This mask can be used to pattern a thick organic underlayer to provide a general bilevel process. Lithographic results on both a 193 microstepper as well as a full field production stepper are presented: resolution down to 0.10 micrometers equal L/S was obtained. A preliminary comparison between PPMS and PP2MS materials is presented, including FTIR results, stability of the films in air and lithographic performance including line edge roughness.

Application of plasma-polymerized methylsilane for 0.18-μm photolithography

Plasma polymerized methylsilane resist films (PPMS) have high sensitivity to short wavelength radiation. The photoinduced oxidation of PPMS films exposed in air forms siloxane network material (called PPMSO), allowing dry development by selective etching of the unexposed regions upon treatment with chlorine based plasmas. Negative-tone patterns of oxidized methylsilane thus formed can be consolidated in a standard resist stripper to form SiO2 like hard mask patterns. In this work, PPMS films are deposited using a commercial single wafer cluster tool dedicated to dielectric deposition. After exposure at 248 or 193 nm, PPMS development is performed in a commercial high density plasma source etcher. Oxide patterns obtained from PPMS films are used for organic resist patterning (bi-layer application) and gate stack patterning (single layer application).

Optimization of Plasma Polymerized Methylsilane process for 248 and 193 nm lithography applications

Optical lithography continues to be investigated as the most interesting approach for achieving sub 0.18 μm design rules. Currently an important effort is going on for single layer resist optimization at 193 nm, while some work is also performed to investigate the potential of top surface imaging schemes. A CVD photoresist currently known as Plasma Polymerized Methylsilane (PPMS) can provide a completely dry photolithographic process, useful at 248 and 193 nm. Negative tone patterns can be developed using Cl 2 -based plasma development allowing the resulting PPMSO patterns to be used as SiO 2 patterns. Up to now, PPMS film deposition and development have been achieved using single step recipes. A single step CVD deposition process provides a film whose composition is identical through out the all thickness whereas the photo-oxidation process induces a gradient of oxidation in the PPMSO film. In this work, we show that a significant improvement of the development can be achieved using a multi-step etching recipe which takes into account the oxidation gradient (and therefore etching resistance) throughout the PPMSO film thickness. Similarly, a significant improvement is performed using a two step CVD recipe. A very photosensitive PPMS film can be deposited on top of a non photosensitive PPMS film, allowing the oxygen incorporation to be limited to the photosensitive film, and therefore limiting the partial oxidation between dense lines in the top photosensitive layer. Comparison between single and bi-layer CVD processes and single and multi-step etching recipes will be presented at 248 nm.

Role of surface tension in silylation processes

The DESIRER process has been proposed as an attractive solution to lithographic problems, combining the performance of multilayer systems to the simplicity of monolayer processes. Despite the large number of studies devoted to this type of process, the various mechanisms involved during the silylation and dry development steps are not yet totally understood. The first part of the paper deals with the changes in solubility of the resist layer before and after silylation and suggests that the polarity of the resist is modified during the process. Surface tension measurements are then reported in order to quantitatively evaluate the changes in polarity of the silylated resist. Finally it is shown that the work of adhesion between silylated and non-silylated material can easily explain both the stability of the silylated islands during the HMDS process and the motion of these silylated areas during the dry development step.

CVD photoresist performance for 248-nm lithography

Some of the major limitations of top surface imaging schemes are now well documented: critical dimension (CD) control across the wafer can be a serious issue as well as line edge roughness (LER). A primary focus of our work has been to investigate the performance of the 248 nm bi-level negative tone approach of the CVD photoresist process based on the plasma polymerization of methylsilane. In this paper, CD control data within a field and across the wafer are presented. CD control is shown to be very strongly dependent on the uniformity of the development step. The best results are obtained when using straight chlorine for the plasma etch development step.

Study of thin gate oxide etching during plasma patterning of 0.1 µm Si gates

When optimizing a 0.1 μm gate etching process using a standard chemistry and plasma operating conditions, we have observed an unsuspected behavior of thin gate oxides. By combining X-ray Photoelectron Spectroscopy (XPS) and spectroscopic ellipsometry, we have attributed this behavior to reactive species penetration through the thin gate oxides. This phenomenon could play an important role in the sub-0.1 μm CMOS process optimization.

Influence of the nature of the mask on polysilicon gate patterning in high density plasmas

High density plasma etching processes of polysilicon gates on thin gate oxide (4.5 nm) have been studied for sub-quarter micron device fabrication. The influence of the mask material on the etching performance has been investigated using either a photoresist mask or an oxide hard mask. Trenching phenomena can be observed at the edges of the gates with both types of mask. When using a photoresist mask, severe defects are formed in the gate oxide near the polysilicon gate, showing that the gate oxide has been preferentially etched during the process. We show that these defects can be attributed to the trenching induced by the main etching step of the process, which is transferred into the gate oxide before the overetch starts. The transfer of the trenching effect depends strongly on the polysilicon-to-oxide selectivity which is shown to be dependent on the presence of carbon in the process chamber. When replacing the photoresist mask by an oxide hard mask the polysilicon-to-oxide selectivity can be improved by a factor of greater than three. Therefore, the use of an oxide hard mask results in a larger process window without creating undesirable defects in the active areas of the devices.

Melt flow of the silylated areas during the desire process

The DESIRE@ process has been proposed as an attractive solution to lithographic problems, combining the performance of multilayer systems to the simplicity of monolayer processes. Despite the large number of studies devoted to this type of process, the various mechanisms involved during the silylation and dry development steps are not yet totally understood. The effects of substrate heating, occuring during the dry development process, on the viscous strain of the silylated areas have been recently reported (1). The main results are listed hereafter : * The etch rate selectivity between silylated and non-silylated areas decreases from 15 to15 when the film temperature increases from 20 to 100 “C. * RBS measurements confirm the thermally activated diffusion of silylated chains in the novolac matrix. * Silylation induces a net decrease (from 70 to 5°C) of the glass transition temperature of the novolac polymer. Therefore, the so-called polymer fluid state can be reached during etching, and consequently allows the flow of polymer chains one with respect to each other. Thus, it was shown that the top silylated material can spread and coat the sidewalls of the pattern during the dry development step.