Olivier Rits

A parallel optical interconnect link with on-chip optical access

This paper describes a complete technology family for parallel optical interconnect systems. Key features are the two-dimensional on-chip optical access and the development of a complete optical pathway. This covers both chip-to-chip links on a single boards, chip-to-chip links over an optical backpanel, and even system-to-system interconnects. Therefore it is a scalable technology. The design of all parts of the link, and the integration of parallel optical interconnect systems in the design flow of electronic systems is presented in this paper.

Synchronous Parallel Optical I/O on CMOS: A Case Study of the Uniformity Issue

Short-range parallel optical interconnect between integrated circuits can alleviate bandwidth, power, and packaging density issues that are associated with low-latency high-bandwidth input-output over electrical interconnect. In this paper, we evaluate the option of using true source-synchronous signaling over optical interconnect with a large number of channels, reducing the substantial per-channel clock synchronization circuitry to one instance. We also look into dc-unbalanced signaling to remove the need for data coding. Uniformity across channels is key to the feasibility of such an approach. An actual 64-channel parallel optical interconnect setup at 1.25 Gb/s/channel is examined, and models for the performance and uniformity of the different constituent parts of the interconnect are drawn up. Major attention is given to the statistical modeling of the coupling efficiency between a vertical cavity surface emitting laser array and a multifiber connector. Although derived in the context of a uniformity study, the stochastic models and the modeling approach are valuable in their own right. In our case study, the usage of a common logic threshold across all channels, which is required for dc-unbalanced signaling, appears infeasible after all models are combined. Efficient true source-synchronous signaling turns out to be within reach in carefully designed systems.

2D parallel optical interconnects between CMOS ICs

The CMOS IC industry thrives on the down-scaling drive for ever smaller transistors, leading to faster, smaller and more complex digital systems. These ICs are interconnected by electrical tracks running on Printed Circuit Boards. Due to different frequency-dependent sources of signal degradation, the performance of these electrical interconnects lags behind the IC performance. As the electrical interconnect bottleneck increasingly impacts overall system performance, the interest in optical interconnects at the inter-chip level is growing. An important question to answer is how and where such optical interconnects should be implemented. Therefore, we first discuss the weaknesses of electrical interconnects and the potential benefits of optical interconnects. From this we then consider the implications on the introduction of optical interconnects and we argue why integration is of key importance for the successful introduction of optical interconnects at this level. Finally we describe how we have implemented optical inter-chip interconnects in a demonstrator system and go into more detail on the different levels of integration in this demonstrator system.