Michiel De Wilde

A parallel optical interconnect link with on-chip optical access

This paper describes a complete technology family for parallel optical interconnect systems. Key features are the two-dimensional on-chip optical access and the development of a complete optical pathway. This covers both chip-to-chip links on a single boards, chip-to-chip links over an optical backpanel, and even system-to-system interconnects. Therefore it is a scalable technology. The design of all parts of the link, and the integration of parallel optical interconnect systems in the design flow of electronic systems is presented in this paper.

Circuit-level simulation approach to analyze system-level behavior of VCSEL-based optical interconnects

In order to satisfy the increasing demand for interchip interconnect bandwidth, a number of current research projects are concentrating on the use of waveguided optical interconnect arrays to span PCB-range distances. To accelerate system design and technology development, CAD tools for the design and the simulation of the interconnects are indispensable. We are developing a design methodology for optical inter-chip interconnects, to produce a tool for assisting system designers on deciding on product and parameter options for the different interconnect building blocks. A mandatory first step in this methodology development concerns the investigation of the combined impact of individual product and parameter variations on system-level interconnect system properties. Accurately predicting some interconnect properties requires analog simulation of the full electrical-optical-electrical links. Detailed models for the link building blocks involving geometrical calculations are much too slow for this purpose. Circuit-level simulation tools, with appropriate model descriptions, are much more suitable. In this paper, we describe our framework for the joint simulation of the entire optical interconnect with a mixed analog/digital system. We discuss in detail a number of issues that are involved with the implementation of circuit-level simulation models in the analog modelling language Verilog-AMS, and show a link simulation example.

AQUASUN : adaptive window query processing in CAD applications for physical design and verification

CAD applications for physical design and verification very often require enumerating all layout objects whose bounding box intersects an axis-aligned rectangular area. A number of multidimensional access methods exist to process such window queries. The performance of some important design and verification algorithms heavily depends on the processing speed of the used access method. For complex layouts, these methods require huge amounts of resident memory to attain this speed.In this paper, we present a new access method called AQUASUN, which brings a significant query processing performance improvement over other adaptive methods---methods which can cope with a continuously changing layout. These methods generally descend from the database world and are designed to perform the equivalent query in n-dimensional space. Our method is specifically tailored to two dimensions, exploiting 2D optimisations that significantly accelerate window queries within oblong objects like PCB tracks. Furthermore, AQUASUN makes use of an efficient compression technique which greatly cuts down on memory usage.

Sense and nonsense of logic-level optical interconnect: reflections on an experiment

Centimeter-range high-density optical interconnect between chips is coming into reach with current optical interconnect technology. Many theoretical studies have identified several good reasons why to use such types of interconnect as a replacement of various layers of the traditional electronic interconnect hierarchy. However, the true feasibility and usefulness of optical interconnects can only be established by actually building and evaluating them in a real system setting. This contribution reports on our experience in using short-range high-density optical inter-chip interconnects. It is based on the design and construction of a fully functional optoelectronic demonstrator system. We discuss the rationale for building the demonstrator in the first place, the implications of using many low-level optical interconnections in electronic systems, and the degree to which our expectations have been fulfilled by the demonstrator. The detailed description of the architecture, design and implementation of the demonstrator is not presented here, but can be found elsewhere in this issue.